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Found 7 results

  1. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  2. In Vivado (2021.2) I have created a new project for the ZedBoard that includes: MicroBlaze in microcontroller configuration with 128KiB local memory AXI interrupt controller AXI timer AXI GPIO (x2) MicroBlaze Debug Module UARTlite When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively): set_property PACKAGE_PIN Y10 [get_ports {uart_rtl_rxd}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {uart_rtl_txd}]; # "JA4" Now I get the following during placement ("Implementation/Place Design/Pin Planning/IO Standard"): [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs: uart_rtl_rxd (LVCMOS18, requiring VCCO=1.800) and sys_clock (LVCMOS33, requiring VCCO=3.300) All of the Pmod connections for the PL appear to be in Bank 13, which is 3.3v, so I am looking for a way to tell Vivado that I want "uart_rtl_rxd" and "uart_rtl_txd" to be 3.3V, and while I'm at it, add any necessary pull-ups/pull-downs. I found out about the "Pmod bridge" IP and installed the unpacked "vivado-library-zmod-v1-2091.1-2" into the IP repositories, and have tried to add "pmod bridge 1.1", routed the "tx_0" and "rx_0" from the UART Lite as I saw in one example, but can't figure out how to assign the "Pmod_out_0" I end up with to a specific Pmod connector. The tutorial at https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/2018.2 indicates that the "board" tab should have the Pmod interfaces listed, but they don't appear for the ZedBoard. I have attached the block design that removed the direct connection of the uartlite tx and rx signals to pins and added the Diligent Pmod Bridge IP as "tutorial_1.tcl". I am really out of my depth here. I will continue to seek answers via Google and forum searches, but any suggestions would be appreciated. Thanks. tutorial_1.tcl
  3. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it delivers 594MHz and 74.25MHz. 74.25MHz clock is intended to clock buses, microblaze, hdmi_out core 594MHz clocks are intended to clock MPMC core (8 times microblaze clocks). Now for my questions ? : 1/ I am not so sure about the locked/rst chains I designed. Could anyone confirm it is correct or give me suggestions on how to make it good ? 2/ I can no longer use the clock wizard in XPS as I replaced the original clock generator with this core. If I try to launch Clock Wizard in XPS, it complains there is no clock generator core and tells me to add one from the IP Library. My question : is there a way I could "persuade" XPS that my core is a clock generator so that it can calculate and validate timings with this home made core ? 3/ Last (but not least) : the project does generate a bitstream. However I'm quite sure the whole timing part is not processed as it does not work. No signal from hdmi_out when using this core. The number of files produced during bitstream generation is awfully low (400 instead of more than 2300 when generating with original design). So I guess I must have missed something : probably the time constraints. The problem is that I have absolutely no idea where to begin with this as I have never ever coded timing constrains.. I would really appreciate any guidance on how to solve these problems. Cheers. N.B : this is an XPS project under ISE 14.7.
  4. Hi All, I am working with a ZedBoard trying to test the output functionality of the Pmod headers. The Pmod headers on this ZedBoard have worked in the past, however, when I try to work with them now it appears that they do not transmit any output data. I've tried this for all four programmable logic accessible headers (JA1, JB1, JC1, JD1). When I assign the output to the LEDs I am able to see the output successfully, but it does not come through the Pmod headers. Here is a very simple HDL file and constraints file that I'm using on my ZedBoard that should produce output on the Pmod headers. HDL File (dut.v): `timescale 1ns / 1ps module dut( output PMOD ); assign PMOD = 1; endmodule Constraints File Contents (constraints.xdc): # ---------------------------------------------------------------------------- # JA Pmod - Bank 13 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN Y11 [get_ports {PMOD}]; # "JA1" set_property PACKAGE_PIN AA8 [get_ports {PMOD}]; # "JA10" set_property PACKAGE_PIN AA11 [get_ports {PMOD}]; # "JA2" set_property PACKAGE_PIN Y10 [get_ports {PMOD}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {PMOD}]; # "JA4" set_property PACKAGE_PIN AB11 [get_ports {PMOD}]; # "JA7" set_property PACKAGE_PIN AB10 [get_ports {PMOD}]; # "JA8" set_property PACKAGE_PIN AB9 [get_ports {PMOD}]; # "JA9" # ---------------------------------------------------------------------------- # JB Pmod - Bank 13 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN W12 [get_ports {PMOD}]; # "JB1" set_property PACKAGE_PIN W11 [get_ports {PMOD}]; # "JB2" set_property PACKAGE_PIN V10 [get_ports {PMOD}]; # "JB3" set_property PACKAGE_PIN W8 [get_ports {PMOD}]; # "JB4" set_property PACKAGE_PIN V12 [get_ports {PMOD}]; # "JB7" set_property PACKAGE_PIN W10 [get_ports {PMOD}]; # "JB8" set_property PACKAGE_PIN V9 [get_ports {PMOD}]; # "JB9" set_property PACKAGE_PIN V8 [get_ports {PMOD}]; # "JB10" # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; Has anyone experienced this faulty behavior? Are they any workarounds or solutions?
  5. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[1]}] set_property -dict {PACKAGE_PIN L18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[1]}] set_property -dict {PACKAGE_PIN M14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[0]}] set_property -dict {PACKAGE_PIN N14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[0]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[2]}] set_property -dict {PACKAGE_PIN M17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[2]}] set_property -dict {PACKAGE_PIN M18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[3]}] set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[3]}] This works great on S7. The problem comes in when trying to use my HDMI PMOD with my new Arty A7 board. I looked up the PMOD pins, and got // for the A7: // top row is D12, A11, B11, G13 // bot row is K16, A18, B18, D13 // so TMDS1 is {B11, G13} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {D12, A11} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {B18, D13} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {K16, A18} = {hdmi_out_n[3], hdmi_out_p[3]} and my constraints look like this set_property -dict { PACKAGE_PIN G13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[1] }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[1] }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[0] }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[0] }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[2] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[2] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[3] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[3] }]; #IO_25_15 Sch=ja[10] So as far as I can tell, I made sure that the same JA pins map to what the HDMI PMOD expects. All the RTL code is the same. But now I get these errors Not sure if this is one error causing another, or two different errors. First of all, it seems like the PMOD negative and positive pins are somehow swapped. Or at least that's how I am interpreting ”the positive port (P-side) of a differential pair cannot be placed on a negative package pin”. The other mystery is site IOB_X0Y149 not being part of a differential pair. Any help is appreciated, since this is my first foray into worrying about pin polarity
  6. Hi What is the difference between using the boards file (when starting a project) vs the constraints file (for the board from Digilent)? For example if I add a GPIO IP to the block design, I can select an item from the board (as shown in the boards tab) to assign it to (without uncommenting the items in the constraints file). Thanks
  7. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY. A few questions come to mind: Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors... Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.