Weevil

Question: AD2 .net UWP

By Weevil, September 9, 2020 in Test and Measurement

• Awaiting best answer

Question: cmod-A7 SPI-bootloader starts with second connection

By Weevil, December 6, 2018 in FPGA

• Has best answer

• cmod-a7
• spi-flash
• (and 1 more)

  Tagged with:

  • cmod-a7
  • spi-flash
  • bootloader

Question: SPI-Flash CmodA7-35T Vivado 2017.3

By Weevil, October 28, 2018 in FPGA

• Has best answer

• cmoda7
• vivado
• (and 1 more)

  Tagged with:

  • cmoda7
  • vivado
  • artix-7

Question: 32bit data transfer using uartlite

By Weevil, March 18, 2018 in FPGA

• Awaiting best answer

• uart
• python
• (and 2 more)

  Tagged with:

  • uart
  • python
  • dma
  • cmod a7

Question: FFT

By Weevil, February 24, 2018 in FPGA

• Awaiting best answer

• fft

Question: Axi DMA timing

By Weevil, February 5, 2018 in FPGA

• Awaiting best answer

• arty
• dma

Question: Streaming FFT data

By Weevil, January 2, 2018 in FPGA

• Awaiting best answer

• ddr
• uart
• (and 2 more)

  Tagged with:

  • ddr
  • uart
  • dma
  • microblaze

Question: Arty adjustable clock with Microblaze and Vivado SDK

By Weevil, December 6, 2017 in FPGA

• Awaiting best answer

• arty
• microblaze
• (and 1 more)

  Tagged with:

  • arty
  • microblaze
  • vivado sdk

Question: AD2, record continously using whole buffer

By Weevil, March 26, 2017 in Test and Measurement

• Awaiting best answer

• analog discovery 2
• record

Question: Analog Discovery 2 - Filter

By Weevil, September 23, 2016 in Test and Measurement

• Awaiting best answer

Question: Analog Discovery 2, gap between aquisition

By Weevil, February 8, 2017 in Test and Measurement

• Awaiting best answer

Question: Trigger with AnalogOut/DigitalOut the AnalogIn

By Weevil, September 28, 2016 in Test and Measurement

• Awaiting best answer