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Found 5 results

  1. Hello, I am building a project where I need to use DMA to transfer data from PL to PS. I am following the tutorial given here. My board is Eclypse-Z7 and the application is a petalinux project. The project is working fine for small data transfers. When the size of the data is more than ~130kB, it fails. Can it be caused by lack of large contiguous memory in DDR? The width of the address bus is set to 26 in the AXI DMA IP. To debug the issue, i have slowed down the data which the AXI Stream sends to the DMA. For small data size, the DMA runs for a time enough to acquire the data from the AXI stream. When the number of bytes to be transferred is set to a high value, DMA stops immediately. Can anyone suggest ways to overcome this?
  2. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
  3. I am trying to this project from . But form me recording never stops. I also, took reference from the above link of Christian, but it's still not working for me. Can anyone help to fix this thing for me. My issue is same as Christian. Also can anyone help me to set J5 to JTAG. Playback is going well, but recording never stops. Please check the images attached.
  4. Hey Digilent, I've successfully run the low_level_zmod_adc_dac demo on my board with a ADC and DAC ZMOD. I next decided to run the zmod_dac demo using both petalinux and baremetal. I was able to program the FPGA and also run the code, however every time it attempts to allocate a buffer to transfer the waveform via AXI DMA malloc is returning a 0/NULL value for the buffer address. If I am correct this means that malloc is unable to obtain memory. I'm running this demo as is directly from your git repo. The error that occurs due to this 0 buffer address varies, for petalinux it causes a memory violation error when it tries to copy the waveform to the buffer. For bare metal it copies fine, but then the AXI DMA copy never completes presumably due to the bad 0 address. Do you have any tips for me on how to get this demo running? If there is any additional information I can provide just let me know. I did find it curious that fnAllocBuffer takes an "addr" corresponding to the dmaAddr on the zmod but then doesn't use it for anything, could that be related? Thanks! void* fnAllocBuffer(uintptr_t addr, size_t size) { uint32_t *buf = (uint32_t *)malloc(size); return buf; }
  5. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.