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Found 6 results

  1. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high throughput and low latency on this board? Is it possible to extend the board with PCIe? To get the full Ethernet capacity, could you please advise if purchasing a TEMAC IP license is advised and at what price? What are the alternative options and industry standards? Many thanks YM
  2. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  3. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  4. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS mandate 2.5V rail voltage in 7Series devices. Is it possible to alter the feedback resistor network for FB1 (shown on pg. 10 of https://reference.digilentinc.com/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_b.pdf) to convert Vcco 3.3V to 2.5V? I believe by reducing R200 from 31.6K to 21.5K, 2.5V output from channel 1 of ADP5052 is achievable. Please confirm that there are no unintended consequences here. Also, I worry about signal integrity when routing differential pairs through standard 0.1" pin headers. Is this a valid concern for my frequencies of interest (50 ~ 200MHz)? I appreciate your input.
  5. Hello, I'm looking into storing data from an ADC system read through an FPGA to an SD card at 3.5 Mbps. I'd prefer not to use a processor. It looks like I could plug the PmodSD into a CMOD A7 (for example). I've found some discussions of directly writing to an SD card on the Digilent Forum, and some links to VHDL to do this; I especially like this code: https://github.com/xesscorp/VHDL_Lib/blob/master/SDCard.vhd?_ga=2.101734593.1593613684.1574706372-1261715882.1574452484 In this discussion: D@n says he has been able to write to an SD card at 8 Mbps, so that would be fast enough for me. However, in this discussion: BenBog says he can't write faster than 1 Mbps. Is this because he is going through a linux driver from the MicroBlaze? Once the write gets going, the SPI clock used by the SD card is 25 MHz, so I'm wondering what limits the achievable write speed to much less than 25 Mbps? Is it because the write is limited to 512 byte blocks and then you have to set up a new write sequence? If one writes to an SD card directly with vhdl through SPI you obviously don't generate a file system; I presume if you use a formatted SD card the file formatting gets overwritten. This would be fine, but I'm wondering how/if one can then read this SD card on a computer? Presumably when you plug in such a card the OS will see that the card isn't formatted and won't know what to do with it. Is there some way to still get the data off the card? thanks in advance, Paul Smith Indiana University Physics
  6. TeslaCrytpo

    CMOD S7 STP FIle

    There is a 3D stp file available for CMOD A7 board, but I do not see one for the CMOD S7 board. Is one available? Thanks. James
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