This sounds like one of those XY problems. You might get better help if you explain the wider context of what you want to do with this counter.
Having said that, a 16 bit synchronous counter running at 200 Mhz in the FPGA fabric is trivial using the RTL design flow. However you won't be able to get 200 Mhz 3.3V CMOS signals out though the uncontrolled impedance IO pins of a CMOD module reliably. Maybe at 20 Mhz this would work. If you could put whatever is capturing this output into the fabric instead of going over IO pins it might work, but alas it is hard to offer suggestions without understanding what you are actually trying to do. Even synchronous counter pins will not change at exactly the same time, so how the receiving device is clocked is critical.
Regarding the 12 Mhz clock oscillator on the CMOD devices, that is normally meant to serve as a reference to a clock management tile in the FPGA that multiplies it up to the desired internal 200 Mhz frequency. You can use the IP wizard to synthesize a clock multiplier and then instantiate it into your RTL code to give you the frequency you want.
Cheers,
JC