QuailJohn

I think you may be misreading the XADC spec. It says that the XADC is powered by the 1.8V vccaux bus. That is not the same as saying the pins should be configured for 1.8V digital logic. It appears you have to give it the same digital IO standard as the other pins so the tools don't freak out, as in Viktor's example.

This sounds like one of those XY problems. You might get better help if you explain the wider context of what you want to do with this counter. Having said that, a 16 bit synchronous counter running at 200 Mhz in the FPGA fabric is trivial using the RTL design flow. However you won't be able to get 200 Mhz 3.3V CMOS signals out though the uncontrolled impedance IO pins of a CMOD module reliably. Maybe at 20 Mhz this would work. If you could put whatever is capturing this output into the fabric instead of going over IO pins it might work, but alas it is hard to offer suggestions without understanding what you are actually trying to do. Even synchronous counter pins will not change at exactly the same time, so how the receiving device is clocked is critical. Regarding the 12 Mhz clock oscillator on the CMOD devices, that is normally meant to serve as a reference to a clock management tile in the FPGA that multiplies it up to the desired internal 200 Mhz frequency. You can use the IP wizard to synthesize a clock multiplier and then instantiate it into your RTL code to give you the frequency you want. Cheers, JC

I like the fact that there is no DDR or hard processor cores on the CMOD-A7. Just the fabric. Simple and clean. My number one request would be more than a single ground pin. I know it's never going to have really high speed IO, but give us more than a single ground pin in the corner.

To get a useful answer you need to post some actual information about your design, such as how the XADC is connected up within it, and the settings you used for the XADC wizard. Given the question you posted, the best one can say is that you are probably doing something wrong in the XADC wizard or how you are instantiating the XADC module in your design.

Is your transform length an exact integer multiple of the 10 Mhz input signal period? If not, this is expected behavior as you are seeing the spectrum of the input signal truncated to the transform length. Google "fft windowing bin leakage".