UMDC

Hi, I don't have any relevant experience with FPGAs -- I did Verilog projects in college long ago, but have never done anything with actual hardware. I'm hoping someone with experience could help me out, by offering an informed guess whether or not this could be possible with the Cmod A7: I need a 16-bit synchronous binary counter that can run up to 200 MHz (3v3 cmos). That's pretty much it... clock and reset in, then 16 output pins that indicate how many clock cycles occurred since reset or overflow. And by synchronous, I mean, the outputs should all change at once, rather than toggling like a ripple counter. It could latch out on the falling clock edge, the next rising edge, or after a fixed delay -- I don't care. In fact, it can even ripple, so long as it does it within one clock cycle. But I don't know enough about FPGAs to parse out whether this speed is possible, from the datasheet. I can presumably figure out how to make it do this, if it is possible. But it would take me a great deal of time, even just to figure out if it is possible. Also grateful for suggestions if you know a better way to do this... I had assumed there would be a cmos counter chip that could do this easily but can't find one. Thanks!