Is this possible with a Cmod A7-35T?

[UMDC]

Hi, I don't have any relevant experience with FPGAs -- I did Verilog projects in college long ago, but have never done anything with actual hardware.

I'm hoping someone with experience could help me out, by offering an informed guess whether or not this could be possible with the Cmod A7: 

I need a 16-bit synchronous binary counter that can run up to 200 MHz (3v3 cmos).  That's pretty much it... clock and reset in, then 16 output pins that indicate how many clock cycles occurred since reset or overflow.  And by synchronous, I mean, the outputs should all change at once, rather than toggling like a ripple counter. It could latch out on the falling clock edge, the next rising edge, or after a fixed delay -- I don't care.  In fact, it can even ripple, so long as it does it within one clock cycle.  But I don't know enough about FPGAs to parse out whether this speed is possible, from the datasheet.  

I can presumably figure out how to make it do this, if it is possible.  But it would take me a great deal of time, even just to figure out if it is possible.

Also grateful for suggestions if you know a better way to do this... I had assumed there would be a cmos counter chip that could do this easily but can't find one.  

Thanks!

[kerryn]

Hi,

I'm using the CMod A7.    It's main clock appears to be 12MHz,  so I doubt it would be able to do it.

I'm only new to FPGA myself,  but I would suggest you take a look at the main clock rates they're running.

I imagine you're going to need main clock at a 1GHz or more to be able to do something like what you describe.

bye for now

KB

[QuailJohn]

This sounds like one of those XY problems. You might get better help if you explain the wider context of what you want to do with this counter.

Having said that,  a 16 bit synchronous counter running at 200 Mhz in the FPGA fabric is trivial using the RTL design flow. However you won't be able to get 200 Mhz 3.3V CMOS signals out though the uncontrolled impedance IO pins of a CMOD module reliably. Maybe at 20 Mhz this would work. If you could put whatever is capturing this output into the fabric instead of going over IO pins it might work, but alas it is hard to offer suggestions without understanding what you are actually trying to do. Even synchronous counter pins will not change at exactly the same time, so how the receiving device is clocked is critical.

Regarding the 12 Mhz clock oscillator on the CMOD devices, that is normally meant to serve as a reference to a clock management tile in the FPGA that multiplies it up to the desired internal 200 Mhz frequency. You can use the IP wizard to synthesize a clock multiplier and then instantiate it into your RTL code to give you the frequency you want.

Cheers,

JC