How to use the single ended analogue inputs on the ARTYZ720

[RobertDJordan]

Hello, I am trying to get the Single-ended analog inputs working (CK_A0...) with the XADC, but can only find examples using the differential inputs.

This example looks to use the differential inputs (which i can get running and it works work fine for me)
https://github.com/Digilent/Arty-Z7-20-xadc/tree/master

but when i attempt to connect the pins that are used for CK_A0 ect... i get a warning about having mixed voltages on the bank
 

[Place 30-372] Bank 35 has terminals with incompatible standards:
Incompatible Pair of IO Standards: (IN of IO Standard LVCMOS33) & (IN of IO Standard LVCMOS18) have incompatible Vccs
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  In   Bank: 35 Placed GClock :
	Term: clk
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
	Term:  xa_n[0]
	Term:  xa_n[1]
	Term:  xa_p[0]
	Term:  xa_p[1]

Incompatible Pair of IO Standards: (IN of IO Standard LVCMOS18) & (IN of IO Standard LVCMOS33) have incompatible Vccs
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
	Term:  xa_n[0]
	Term:  xa_n[1]
	Term:  xa_p[0]
	Term:  xa_p[1]
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  In   Bank: 35 Placed :
	Term:  sw[0]
	Term:  and sw[1]

I checked the XADC guide and it looks like these pins should run at 1v8, how can i use them if there are other things like switches, and the clock on that bus running at 3v3?

Thanks

Any help is appreciated

[Viktor Nikolov]

I can offer a test project I recently created to test single-ended XADC with DMA. See the attached Vivado 2023.1 HW project and export of the Vitis 2023.1 workspace.
The project is for Cora Z7-7S, but it can be easily re-generated for Arty-Z7 (the constraints file may need a modification, though).

I first created the HW design following the Vivado design part of this tutorial: Signal Processing with XADC and PYNQ - Hackster.io
However, this tutorial covers only differential XADC input, so it took some trial and error to get it to work with single-ended input.

If I remember well, I did the following steps:

• In the XADC Wizard IP configuration, I set Startup Channel Selection to Single Channel.
• On the Single Channel tab, I then selected "VAUXP1 VPAUXN1". And I unchecked the "Bipolar" check box to set unipolar (single-ended) mode.
• Signal Vaux1 appeared on the XADC Wizard. I right-clicked it and selected Make External. This created the input signal Vaux1_0 in the diagram, connected to Vaux1 on the XADC Wizard.
• I then uncommented the following lines in the Cora-Z7-7S-Master.xdc:

set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_p  }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_n  }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]

With that, I got no errors for the Incompatible Pair of IO Standards.

Edit: The constraints look like they define a differential signal; however, on Cora Z7, VAUX1_N is connected to GND, and VAUX1_P is connected to the board pin labeled A0, as explained in the reference manual.

XDAC_DMA_test_hw.zip vitis_export_archive.ide.zip

Edited April 30 by Viktor Nikolov

[artvvb]

2 hours ago, Viktor Nikolov said:

The project is for Cora Z7-7S, but it can be easily re-generated for Arty-Z7 (the constraints file may need a modification, though).

One note to add, Zynq PS settings also differ, which can cause trouble when porting a project between boards. There are some options for how to do the port, but the easiest is usually to rebuild the block design from scratch in a new project. Alternatively, it may be possible to export a Zynq preset after doing block automation in a new project, and apply that preset to the project targeting the original board.

[QuailJohn]

I think you may be misreading the XADC spec. It says that the XADC is powered by the 1.8V vccaux bus. That is not the same as saying the pins should be configured for 1.8V digital logic. It appears you have to give it the same digital IO standard as the other pins so the tools don't freak out, as in Viktor's example.