JColvin

Hi @gaetan, Unfortunately, Digilent does not have Mean Time Between Failures for any of our products, Cmod A7 or otherwise. Thanks, JColvin

Good choice; only one of us is the WaveForms developer and its not me.

Hello, So, the 1.5 A total for the 5 V rail that I mentioned is listed in Table 7.1.1 in the USB104 A7 Reference Manual (https://digilent.com/reference/programmable-logic/usb104a7/reference-manual#zmod_port), is not a SYZYGY Specification. It is a design choice made by Digilent. You can see that the SYZYGY 5 V rail is limited to 1.5 A on the first page of the USB107 A7 schematic in the power tree diagram. I am not certain where you are getting from the Power Rail Specifications Table 1.2.1 that the 5 V rail can supply 3 amps. The line entry I presume you are looking at is for the 3.3 V rail, which is derived from the 5 V rail, as noted by the "upstream net name" in the second column. Regardless, you cannot supply more than 2 amps to the 5 V rail as per Table 4.1 in the SYZYGY (not Digilent) Specifications: http://syzygyfpga.io/wp-content/uploads/2023/09/Syzygy-Specification-V1p1p1.pdf. The reason why Digilent provides a 5 V 6 Amp power supply (30 Watts total) is to meet the power budget outlined in Table 1.2.1 as each rail (the Net Name column) is derived from the VCC5V0 net. Let me know if you have any questions. Thanks, JColvin

Hi @sand, You'll be wanting FDwfDigitalIOOutputEnableSet and FDwfDigitalIOOutputSet which are defined in the Digital IO section (section 8) of the WaveForms SDK Reference Manual. DigitalIO.py in the samples folder uses these two functions, enabling DIO 0 to 7 as outputs and then setting IO pins 2 and 5 as logic high. Let me know if you have any questions (or if I misunderstood what you are wanting to do). Thanks, JColvin

Hi @DavidD, There are a couple of likely culprits causing this issue. One is a USB cable of insufficient quality or bad connection (bad connection also could happen if you are routing the cable though an already busy USB hub). The second could be inconsistent power, potentially from the USB cable (also an issue with a busy). What I would personally be attempting to resolve this is to try both a different USB cable and USB port (I have had both fail on me before). Let me know what you find out. Thanks, JColvin

Welcome to the Forum!

Hello, Your question is valid. I asked one of the hardware engineers to see if there was some insight that I was missing, but they let me know that the 6-pin external JTAG header is purely as a backup option. You can still load bitstreams/.bins from the Vivado Hardware Manager as well as applications from Vitis (I loaded an HDMI example onto a Zybo-Z7 via a JTAG HS2 just now) but you still don't have direct access to UART nor the PS_POR_B pin for processor resets. Let me know if you have any questions. Thanks, JColvin

Hi @Mohamed Kamal, The formulas for the various calculations of the Impedance Analyzer are provided in the WaveForms Help tab: Rs and Xs have some additional clarification in this Forum thread here: As for how to get the 'overall capacitance', both series and parallel models provide the overall capacitance; which model you "should" choose depends on what kind of measurement you are making. This Application Note provides a good overview and addresses this type of question in its FAQ: https://assets.testequity.com/te1/Documents/pdf/series-parallel-impedance-parameters-an.pdf. Let me know if you have any questions. Thanks, JColvin

Hi @Mohamed Kamal, Yes, the load is the DUT in this instance. If you wanted to do short compensation as well, you could modify and add to the the AnalogImpedance_Compensation.py example with the existing functions in the example as well as the FDwfAnalogImpedanceCompGet function described in the WaveForms SDK Reference Manual (section 12, page 116) to maintain the obtained open compensation value. Let me know if you have any questions. Thanks, JColvin

Hi @jayanth mb, The Analog Discovery 3 Resource center contains a number of guides and tutorials on using the different instruments: https://digilent.com/reference/test-and-measurement/analog-discovery-3/start. The Help tab within the WaveForms software (next to the Welcome tab) also contains a wealth of built-in documentation on the different settings for each instrument. Let me know if you have any questions about using the AD3 or the WaveForms software. Thanks, JColvin

Hello, Which hardware device do you have and what version of the WaveForms software do you have? The latest WaveForms is available here: Thanks, JColvin

Hi @aeoijfoiwj, Which product are you using? If you are using something like an Analog Discovery 3, you would need the Digilent Toolbox for MATLAB; there is a guide for this available here: https://digilent.com/reference/test-and-measurement/guides/matlab-getting-started. Thanks, JColvin

Hi @FPGA, I have sent you a PM. Thanks, JColvin

Hi @Dr.J, Okay, I understand the confusion. I have updated that box on the Resource Center to better clarify that this specification is for the VIO ports. Regardless, I would defer to the dedicated section in the Reference Manual, https://digilent.com/reference/programmable-logic/usb104a7/reference-manual#zmod_port, for specifics. Though I suppose it's worth noting that the Table 7.1.1 lists 1.0 A (VIO Group 1) on the VIO Supply Current rather than 1.2 A, but this stems from the VADJ rail that the VIO supply comes from (page 11 of the schematic, https://digilent.s3-us-west-2.amazonaws.com/resources/programmable-logic/usb104a7/USB104_A7_sch.pdf) can supply 1.2 A of current, but only the SYZYGY port itself and a lone LED indicator draws from this supply rail. Let me know if you have any questions. Thanks, JColvin

Hello, Realistically, there won't be anything helpful in this particular regard. The connection from the external JTAG J13 to the FPGA is shown on page 9 of the schematic: https://files.digilent.com/resources/programmable-logic/zybo-z7/zybo-z7-d1-sch.pdf. I had blanked on the fact that because you are using an external debugger that you would be using the external JTAG port, which does not provide access to the PS_POR_B pin which is needed for resets; this is explained in a bit more detail in the Zynq Technical Reference Manual from AMD, UG585: https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM. Let me know if you have any questions. Thanks, JColvin

Hi @Jeong cha, I have sent you a PM. Thanks, JColvin

Hi @weaverdouglas22, Understood. The W1 and W2 labels on the BNC Adapter were chosen because that matched the labels of the two waveform generator channels shown on the plastic of the Analog Discovery 2 and 3. If you have a different labeling scheme in mind that would help make the product more intuitive to users, I would love to hear it so that I can pass it on to R&D. Thanks, JColvin

Hello, I responded to your other thread here: Thanks, JColvin

Hi @Dr.J, Unless I'm mistaken, both 3.3 V and 5 V are available on the USB104A7. The 5 V rail is the SYZ5V0 as noted in Table 1.2.1 in the USB104A7 Reference Manual: https://digilent.com/reference/programmable-logic/usb104a7/reference-manual#power_specifications. You can see this rail on the schematic on page 2 and page 12: https://digilent.s3-us-west-2.amazonaws.com/resources/programmable-logic/usb104a7/USB104_A7_sch.pdf. I'm not sure where you are getting the 1.2 Amp requirement for the 5 V supply, as it there is explicitly no minimum current requirement listed in Table 9 of the SYZYGY Specification version 1.1.1 from September 2023: https://syzygyfpga.io/specification/, but as per Table 7.1.1 in the USB104A7 Reference Manual the 5 V rail will supply up to 1.5 A in total: https://digilent.com/reference/programmable-logic/usb104a7/reference-manual#zmod_port. The 1.2 V to 3.3 V is for the VIO supply voltage, which is within the recommended range also noted in the same Table 9 in the SYZYGY Specification 1.1.1. Please let me know if I am misunderstanding your question. Thanks, JColvin Edit: After re-reading, I see you were referring to the main landing page/Resource Center for the USB104A7. I have updated that page to better indicate that it is the VIO supplies specifically that are 1.2 to 3.3 V.

Digilent also provides a board file preset that will correctly configure the Zynq block with its various on board peripherals, including UART, for you; https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files. When adding the Zynq block to the Block Design, you'll just need to check the Apply Board Preset box (visual in the Add a Zynq processor dropdown here: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_a_processor_to_a_block_design). Let me know if you have any questions. Thanks, JColvin

Hi @Danny Cote, The most consistent way, of course, would be to power cycle the device. Which device and what version of WaveForms are you using? Normally, when you close the WaveForms GUI, the device (more or less) becomes immediately available to use in a separate application or script. Thanks, JColvin

Hi @concept, 1. No, you do not have to unsolder it. There are tri-state buffers that disconnect the FTDI chip from the onboard JTAG nets when the FTDI chip is not open in Adept or Vivado; there are also some series resistors in place to protect circuitry from being damaged, though of course it is up to the end user to avoid deliberately creating drive conflicts. Figure 5 in the JTAG SMT3 Reference Manual shows the basic layout approach: https://digilent.com/reference/programmers/jtag-smt3/reference-manual#example_2interfacing_a_zynq-7000_while_retaining_the_xilinx_jtag_header. 2. You can use a standard straight 6-pin 100 mil header. The staggered layout is so that you can maintain electrical contact without having to solder an external header in. 3(ish). I personally don't often use J8, mostly because a lot of the designs I end up working with implement UART, and I already have a convenient connection to the host computer through J10 with the USB-JTAG circuitry. Let me know if you have any questions. Thanks, JColvin

Hi @Anthocyanina, Thank you for the feedback; you have been heard. I will be sure to communicate this to the team for future T&M devices. Please let me know if you have any additional feedback or questions. Thanks, JColvin

Hi @CJtech2023, Which Digilent product do you have? Your screenshots indicates that you might have the Nexys 4 DDR board, but you also mentioned having an Artix-7 15T FPGA, which is not present on any of the Nexys boards. I want to make sure I do not give you faulty instructions to avoid any chance of accidentally damaging the device. Thanks, JColvin

Hi @Chithambaram Veerappan, A Zybo Z7 will have a silkscreen labeling of "Zybo Z7" and only HDMI ports (the original Zybo had a VGA connector), but I doubt that will be relevant here. I am not familiar with the WaveShare JTAG module, but it looks to be based on (or maybe is) the original Xilinx Platform USB Cable, which might be compatible with the PS_POR_B pin on Zynq devices for the processor via the listed Halt pin, but I am not certain. This seems like the most likely culprit considering that you are having difficulties getting it to configure the ARM core processor side. This thread was for a different JTAG programmer, but you might have some luck following the recommendations in there: Thanks, JColvin