Fadi

Hey Everyone, Has anyone successfully set up the Arty A7 using the 6-pin JTAG connector? If so, what essential information should I be aware of for this configuration?

so you mean to say that after configuration if clock is required we can configure L16 pin as output and use it instead as CCLK_0 cant be accessed directly.

Hello Everyone, Im new to all this so bear with me please. I am studying the schematic of Arty A7 100T board and confused about the connection of CCLK and EMCCLK pins. I read in documentation that EMCCLK pin is used to attach an external clock source to speed up the configuration process when configuring from QSPI. but in the Arty A7 schematic the EMCCLK pin is connected to QSPI_SCK signal that itself is being generated from FPGA through CCLK pin when its working as a Master device. kindly if someone can explain all this it'll be a great help. Thanks