JColvin

Hi @cactuskooler, The power switch (SW8) on the Zedboard is a MS12ANW03 from NKK Switches. Let me know if you have any questions. Thanks, JColvin

Hi @arang, The voltage setting is for all pins; this is a hardware limitation as the Supplies sets the VCCIO_PROG voltage for the banks that all of the pins (DIO and DIN) are connected to. Let us know if you have any questions. Thanks, JColvin

Hello, I got the lwIP Echo Server example working for Arty A7-35 in 2023.1. There were a couple of gotchas that I ran into that you may have already addressed, but I'll list them anyways. - In the Vivado block design, I forgot to connect the AXI EthernetLite interrupt, which caused problems getting an IP addressed assigned via DHCP - In Vitis, I needed to fix the conflicting status error. Basically, comment out the “u16_t status;” line 399 in /design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/microblaze_0/libsrc/lwip213_v1_0/src/contrib/ports/xilinx/netif/xadapter.c save, then rebuild the project. I learned this from Adam Taylor's mention of it on his tweet here: https://twitter.com/ATaylorFPGA/status/1666347512687411200. - I modifying the Platform BSP settings to have lwip213 → temac_adapter_options → py_link_speed be set to 100 Mbps rather than autoconfig (needed if you are not using a DHCP server such a router and are instead manually connecting) After that, I was able to build the project, open up a Telnet connection on port 7 and then had data echo back to me. The longest waiting was for getting the DHCP to assign the IP address, but that didn't take more than 5 seconds or so. Let me know if you have any questions. Thanks, JColvin

Hi @jarvis, I'm a little surprised to hear that the TCP echo server is starting at port 1022 since from my knowledge the lwIP echo server template used in Xilinx SDK/Vitis is port 7 The long delay sounds symptomatic of two potential problems. One is that there is a delay function in place whose time base is off by a few orders of magnitude. The other, which seems more likely to me based on the 60 second timing, is that the echo server reaches an internal timeout and resets itself. I'm working on creating a MicroBlaze based design to test the Echo Server in 2023.1 to see what results I get. Thanks, JColvin

Hello, I'm not familiar with board you mentioned, but if the device uses a Xilinx Zynq 7010 (and otherwise has an appropriate JTAG topology) then it will be compatible as per the JTAG HS2 Reference Manual containing the list of compatible devices provided by AMD: https://digilent.com/reference/programmers/jtag-hs2/reference-manual#supported_target_devices. The main caveat I can think of is that the JTAG HS2 does not have a pin connection for the PS_POR_B to reset the ARM core processor, so you will be limited in that regard for debugging processes for the Zynq board, though you can still load bitstreams. The JTAG HS3 does have this pin however. Edit: I look up this board. There is a physical problem: the 2x7 JTAG header this board has uses 2.54 mm spacing rather than the 2.00 mm spacing that the Digilent JTAG HSx devices and the Xilinx development boards use. You would need some sort of converter to account for this physical difference. This thread discusses some of the options here: Thanks, JColvin

Hi @Dharmendra, The sources and instructions on how to rebuild the Out-of-box material can be found in the Getting Started guide for the Genesys ZU here: https://digilent.com/reference/programmable-logic/genesys-zu/getting-started#rebuilding_the_out-of-box_image. Thanks, JColvin

Hi @Salvador G, The onboard FTDI chip on the Basys 3 allows for JTAG communication; that is how it can configure the FPGA: https://digilent.com/reference/programmable-logic/basys-3/reference-manual#usb-uart_bridge_serial_port. I do not know the specifics of your setup, but the Adept SDK (part of the Adept download: https://digilent.com/reference/software/adept/start) has a JTAG subsection that might be of help to you. Let me know if you have any questions. Thanks, JColvin

HI @Obsidian, You have done everything that I would have attempted. I'm still on Windows 10, but I confirmed with the Adept developer that Adept will work on Windows 11 (or at least they have been using a fresh install of Windows 11 for over a year with no issues). What sort of processor are you running on? An x86-64 or an ARM? Thanks, JColvin

Hi @Joe306, Xilinx/AMD curated and provided the following list of target devices that is supported by the JTAG SMT2, which does include the Versal ACAP: https://digilent.com/reference/programmers/jtag-smt2/reference-manual#supported_target_devices. As for your schematic, I don't see anything problematic. Your ESD diode based on its datasheet has low enough capacitance to not interfere with USB communication and it looks like you have appropriate protection for any in-rush current coming in on the USB., and otherwise more or less matches the example layout shown in Figure 12 in the Reference Manual, https://digilent.com/reference/programmers/jtag-smt2/reference-manual#application_examples. Let me know if you have any questions. Thanks, JColvin

Hi @arang, I believe that only 7-bit addressing is supported, at least as per the post from the developer here: which is also still the case in the latest beta version (3.21.29, https://forum.digilent.com/topic/8908-waveforms-beta-download/) at time of writing. I have not heard any plans to change this. Thanks, JColvin

Welcome to the Forum!

Hi @sminded, Which Digilent board do you have so we can provide some accurate feedback? Thanks, JColvin

Welcome!

Minor follow up, I looked at the UG475 that zygot referenced, and best that I can tell from Chapter 6 Package Marking, the speed grade used to be its own individual line on the 4th row down, just below the lot code (detailed slightly more in Table 6-1). But based on figure 6-4 for the Artix FPGA (and the equivalent figures for the Kintex and Virtex FPGAs), this is the "Legacy Artix-7 Device Package Marking". I'm not certain when this change occurred, but it was a number of years ago as I have Basys 3 Rev C's (Rev D came out in 2021) both with the speed grade marking and without it. Thanks, JColvin

Hi @dsdsd, From what I can recall, no Digilent device uses a FT2232HL. Digilent's programming solution is made exclusively for Digilent boards and so will not be able to restore a different development board from a different manufacturer. In terms of just generically erasing material, FTDI's FT_PROG application may be able to help you, though it is also likely a common reason for the many users that ended up posting on this thread to begin with. Thanks, JColvin

Hi @Taksun, Digilent typically uses the FT2232HQ device (such as is mentioned in the Arty A7 Reference Manual here: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#usb-uart_bridge_serial_port). I have not done any research into the 56-pin variant, nor I am I sure by what you mean that it does not work as a Digilent programmer, as that seems to imply you have already attempted to configure the device, though I do not know how you would have done so. Regardless, I would not be surprised that with the reduction of pins comes a difference in pin layout as well as register configuration, so I would imagine that Digilent's programming solution as it currently exists would be incompatible with the FT2232H-56Q. Thanks, JColvin

Hi @Frank.L, I have sent you a PM. Thanks, JColvin

Hello, I had forgotten to update this thread with the reply I received a week later: Thanks, JColvin

Hi @jfrenzel, I believe this is because you have the Mode dropdown set to "Standard" rather than "3-wire". With the Standard option, it looks like WaveForms still tries to read what is being transmitted on the DQ1 line; as there is no DQ1 line set, this ends up defaulting to all zeros. Let me know if this does not resolve what you are experiencing. Thanks, JColvin

Hello, I have moved your question to a more appropriate section of the Forum where an engineer more experienced with Linux mode on the ADP3450 can provide a more accurate answer than myself. Thanks, JColvin

Hi @john-con, I can confirm that the Arty A7 and Basys 3 both use speed grade 1 components. I'm not certain off hand where you would readily determine this off of the chip labeling itself, but you can see the critical "-1" portion of the FPGA name in the right hand side of their respective Resource Centers, https://digilent.com/reference/programmable-logic/arty-a7/start and https://digilent.com/reference/programmable-logic/basys-3/start, of the "FPGA Part #" row. As far as I know, zygot is correct that only Digilent's Genesys 2 has a speed grade 2 part. Let me know if you have any questions. Thanks, JColvin

Hi @arang, Not in the Protocol tool specifically, but you can adjust the drive strength, slew, and pull values of the IO pins either through the Supplies instrument or through the Settings -> Options -> DIOs tab. I'm not certain what you mean by duty cycle specifically, but you can change both the System Clock frequency that the Digital Discovery uses at large though those same settings, or you can change the frequency of whatever protocol you are using through the (user typeable) dropdown within the Protocol tab of interest as well. Let me know if you have any questions. Thanks, JColvin

Hi @idegani, As far as I am aware, it's not possible to have a particular configuration loaded on power up as the on-board FPGA will not maintain it's configuration once power is disconnected. The workaround that might work for you would be to use the "Continue" option for what the device does when WaveForms is closed within the WaveForms Device Manager. As long as the device is still receiving power (either over USB or via an external supply), the device will continue to operate in whatever configuration/state it was last set in. I routinely use this when I'm testing other devices but want to limit the total USB activity and ports I am using. There are a couple of other threads that discuss this option here: Let me know if you have any questions. Thanks, JColvin

Adding on to what zygot mentioned, you'll find that many mobile phones will also randomize their MAC address when connecting to a WiFi network by default (Android has some information on it here: https://source.android.com/docs/core/connect/wifi-mac-randomization-behavior), because (in my limited understanding of network operation at large) this would be a localized address within that subnet, so the odds of matching somebody elses MAC address within that same small amount of devices is quite small. Regardless, localized or unique MAC, you'll have a bad time if there is a match as the different communication frames will end up at the wrong device, so that neither device works properly. But that is about as far as my knowledge goes on this particular topic.

Hi @CG73, The Analog Discovery 3 does not come with any sort of calibration certificate/report. However, the individual calibration values are stored within the device and can be viewed within the WaveForms Device Manager by clicking the "Calibrate" button. From there you also have the option to individually calibrate different instruments, or to reload the factory calibration as needed for your device. Digilent does not have any specific recommended calibration schedule. There is some additional information in the WaveForms Help tab here: Personally, I recalibrate my device before I start doing a larger project with it. Let me know if you have any questions. Thanks, JColvin