Zufaruu

Thank you, it's already worked now on baremetal. I think I have some mistakes when checkouting to the correct branch. But, is there a way to import the hardware change so that it can be used on linux project? I try to run my linux project, but it's still capped at 4096 samples

Where can I find the vivado project of the DAC1411_Demo to change the DMA configuration? I'm having the same issue when trying to generate signal with more than 4096 samples by following this tutorial. I've tried to recreate the vivado project of this repo, but in the design file, there's only ZYNQ 7 Processing System IP.

Thank you very much for the additional explanation Here, I want to set the trigger level in two conditions, say that the adc starts polling when the level is above 0.3 V and below -0.3 V. Is there any way to accomplish this?

I've just done trial and error ZMODADC1410::acquireTriggeredPolling function and it's already worked

Hello, I want to do an ADC-DAC Loopback Using Eclypse Z7 FPGA Board, ZMOD AWG-1411, and ZMOD ADC-1410, programmed using Xilinx SDK. I generate signal and send it from the DAC to the ADC. However, it turns out that the signal captured by the ADC is randomly shifted and sometimes it doesn't captured the signal (only captures noise signal). I want the ADC dan DAC starts simultaneously so that the ADC can captures the signal with short or fixed delay. Is there any idea how to do that? I follow this DAC and ADC demo linux to create my code below. I've tried to use std::async but it still doesn't work. I assume using ZMODADC1410::acquireTriggeredPolling should do it, but I still don't understand the trigger concept. Any explanation will be appreciated Thank you very much main.cc

Thank you very much for the explanation. It's really helpful and it's worked :D

Hi, i'm currently following this tutorial or demo linux using ZMOD DAC1411 from here. The demo only generates a signal from either channel 1 or channel 2. How to generate signal from both channels? I'm using Eclypse Z7 and Xilinx SDK 2019