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Found 10 results

  1. hello , Can you provide 3D model of : Eclipse Z7 ZMOD ADC DAC there isn't such data on resource center. thanks.
  2. I am trying to make it such that can make my project stay saved on the FPGA. Currently I am re-downloading the bit-stream each time. How do I access the EEPROM such that I am not having to redownload the bitstream. As for the SD card portion, I want to read in data from a large .txt file and was wondering how to access the file data from it, via Vivado. Say I generate a billion numbers and I want to randomly read those values, I would have a giant pre-generated .txt file (or multiple) on the SD card. How would I go about accessing this?
  3. So I'm running into an issue with processing speeds of the following function: value[i] = sqrt(-2*log((rand() % MAX_RAND_VAL)/(MAX_RAND_VAL+1.0)))*cos(TAU*(rand() % MAX_RAND_VAL)/(MAX_RAND_VAL+1.0)) * sigma; I am generating a random number of gaussian distribution for my output voltage. I need to be able to do this and still output speeds of 10MHz. However it seems that this formula takes roughly 100-200us to calculate, no where near the speed at which I need. Would it be possible to generate all my possible data points into an absolutely massive array before hand? I would need the write the program to the SD card so that I can have a multiple gigabyte array. Is this possible? And how would I go about programming to the SD card such that the program runs on power up? I see there is a jumper pin for QSPI/SD/JTAG but I am relatively unfamiliar with these kinds of things, so I am not certain how to program to the SD card (like would I have to call memory addresses there and just further complicate the system?)
  4. Hello, I am building a project where I need to use DMA to transfer data from PL to PS. I am following the tutorial given here. My board is Eclypse-Z7 and the application is a petalinux project. The project is working fine for small data transfers. When the size of the data is more than ~130kB, it fails. Can it be caused by lack of large contiguous memory in DDR? The width of the address bus is set to 26 in the AXI DMA IP. To debug the issue, i have slowed down the data which the AXI Stream sends to the DMA. For small data size, the DMA runs for a time enough to acquire the data from the AXI stream. When the number of bytes to be transferred is set to a high value, DMA stops immediately. Can anyone suggest ways to overcome this?
  5. I am trying to use the DAC1411 on the Eclypse Z7 to output a changing DC signal for different lengths of time. It appears that when I fill the buffer into the DAC, it just repeats that buffer value without allowing it to be updated. Is there a way to overwrite this buffer with new values (like an interrupt or DAC stop)?
  6. The eclypse z7 has a built in random number generator and I was wondering how I can access this for use in a c++ code.
  7. Hi, I’m using a Zedboard and when I run a program in Vitis, weirdly it doesnt work everytime. Inded, for the same program, sometime everything works as expected (uart print are succesfull, gpio: sw and led too) but sometime the done led is blue and the programme does nothing. It’s occurs often when I already did a run and I try to do a second one, but sometimes afer using the board for long it occurs just after power up the board. I try to always build my project before and let the card cool down but sometimes it doesn’t help. When it doesn’t work, many possibilities : The application does absolutly nothing The uart stop in the middle of a printf an error appears like : « Error while launcing program : reset APU.APB AP transaction error, DAP status 0xF0000021 » or « Error while lauching program : no taargets found with « name=~"APU*" ,avalailable targets : 1 DAP (APB AP transaction error, DAP status 0x30000021) 2 xc7z020 » It's the case for all project I have created ... This behavior is very handicapping for my work. If you are any idea please share it ! Regards, Julie
  8. How do you log into the ECLYPSE Z7 and set the baud rate? Having troubles finding any examples on how to do this. I have the username and password to log in the first time. Just not sure how to actually get there.
  9. Hello everyone, I have a problem uploading and debugging my baremetal code on the Eclypse Z7. I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1 (64-bit). Usually it works fine but sometimes the following error message is thrown when clicking on the project -> Debug As -> Launch on Hardware: "ERROR : Memory write error at 0x119000. Asynchronous Data Abort" This is the Vitis Log output: 14:45:30 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 14:45:30 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 14:45:30 INFO : Launching XSCT server: xsct.bat -n -interactive C:\ZZZ_Projekte_Xilinx_FPGA_LOKAL\DIRCM-H_V1_Vitis\Vitis\temp_xsdb_launch_script.tcl 14:45:30 INFO : XSCT server has started successfully. 14:45:30 INFO : Successfully done setting XSCT server connection channel 14:45:30 INFO : plnx-install-location is set to '' 14:45:30 INFO : Successfully done setting workspace for the tool. 14:45:30 INFO : Platform repository initialization has completed. 14:45:31 INFO : Successfully done query RDI_DATADIR 14:45:31 INFO : Registering command handlers for Vitis TCF services 14:48:02 INFO : Connected to target on host '' and port '3121'. 14:48:02 INFO : Jtag cable 'Digilent Eclypse Z7 210393AD74DAA' is selected. 14:48:02 INFO : 'jtag frequency' command is executed. 14:48:03 INFO : Context for 'APU' is selected. 14:48:03 INFO : System reset is completed. 14:48:06 INFO : 'after 3000' command is executed. 14:48:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Eclypse Z7 210393AD74DAA" && level==0 && jtag_device_ctx=="jsn-Eclypse Z7-210393AD74DAA-23727093-0"}' command is executed. 14:48:08 INFO : FPGA configured successfully with bitstream "C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/bitstream/design_1_wrapper.bit" 14:48:08 INFO : Context for 'APU' is selected. 14:48:08 INFO : Hardware design and registers information is loaded from 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa'. 14:48:08 INFO : 'configparams force-mem-access 1' command is executed. 14:48:08 INFO : Context for 'APU' is selected. 14:48:08 INFO : Sourcing of 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/psinit/ps7_init.tcl' is done. 14:48:09 INFO : 'ps7_init' command is executed. 14:48:09 INFO : 'ps7_post_config' command is executed. 14:48:09 INFO : Context for processor 'ps7_cortexa9_0' is selected. 14:48:09 ERROR : Memory write error at 0x119000. Asynchronous Data Abort --> The execution stops here. Usually the error is removed by restarting the Vitis IDE, Vivado and the FPGA board but this time even restarting the computer multiple times doesn't help. I'm glad for any advice. Thanks.
  10. Hi everyone, As you can see in the title, our plan is to connect a Windows 10 host PC running Matlab with the Digilent Eclypse Z7 board. We want to capture analog Data using the Eclypse Z7 and collect it in Matlab using the Data Acquisition Toolbox over USB, using the USB OTG connector on the board. Is it possible in the first place? Is there a Vitis reference project available? Is it possible to make use of the Matlab driver for the Digilent Analog Discovery 2 hardware (using the respective source code for the Eclypse Z7)? Thank you in advance for your help. Best regards, Nick
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