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Found 2 results

  1. Hello, I am using ZMOD DAC with Eclypse Z-7 board, and I have two questions regarding controlling ZMOD DAC 1411 output voltage: 1) How do I switch between the low gain and high gain setting in ZMOD AWG (ZMOD DAC 1411) to shift between +/-1.25V and +/- 5V setting using the ZMOD DAC LLC IP in Vivado? 2) I want to control the output voltage levels of the DAC. How do I change the signed 14-bit values in my Verilog module to achieve the desired output voltage? The reference manual shows the following equation for controlling the 14 bit value: So for example, if I want to have voltages between 0 and 3 V, how do I set CA, CG and Range (which is again related to High/Low gain value from Q1 above) values using LLC IP in Vivado? How do I interpret Vout in this case? The LLC IP shows as follows: Please provide me with some help in this regard. Currently, I am giving between 14'd0 and 14'b01111111111111 and I am only seeing between 0-670 mV on oscilloscope with trigger setting of 50 ohm DC (and ~0-1.3 V with trigger setting of 1 M ohm DC). Please let me know if you need more information from me. Thank you, Nasir
  2. Hello, We have been developing a real time data transfer application using Genesys ZU-3EG boards along with Zmod DAC/ADC pair. We previously built the application on Eclypse boards and now are migrating the design to Genesys boards. In the process, we have discovered that one of the two Genesys boards is failing to power up the DAC and ADC pods regardless of the fact that our designs are running exactly the same initialization protocols for both of them. We have verified this by inserting both the DAC and ADC pods to both Genesys boards and running some tests. On one board (board A), both DAC and ADC pods prove to be working. For DAC, this is verified by seeing DAC output on Oscilloscope when running our TX design, and for ADC, this is verified by giving an external signal to ADC and observing ILA outputs while running our RX design. On the other board (board B), ADC output appears to remain constant as seen in the ILA regardless of whichever signal we provide through the signal generator. Additionally, DAC's low-level controller IP in Vivado has an init_done_n signal which goes low after it is initialized. In the case of the working board (A), we see this signal going low, and the DAC works, but in the case of the non-working board (B), this signal remains high, meaning the DAC configuration is not done, and we don't see any signal at the DAC output. Observing this init_done_n not going low on the DAC in board B actually made us realize the problem after which we ran these additional tests for verification. All jumpers settings of both boards are the same. We are using jtag mode for programming the PL. Finally, it is to be noted that PL and PS are working okay on board B. It's just the DAC and ADC pods that are not responding. What do you believe is the problem? Are we facing a production based error on SYZYGY connector on board B? Any suggestions on how to proceed? Thanks, Nasir