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Found 6 results

  1. hello , Can you provide 3D model of : Eclipse Z7 ZMOD ADC DAC there isn't such data on resource center. thanks.
  2. Hi: When I try to initialize the ADC and DAC in a same void function, the SDK shows me that 'Can't allocate DMAEnv for 40410000'. '40410000' is the address of DMA_DAC_BASE_ADDR. Because of that, DAC cannot generate the correct waveform when ADC works perfect. By the way, it works perfectly when I just use DAC or ADC. Thanks for any suggestion. Update 26th January My project is using the ADC collect the data and compare the data with the threshold, DAC will generate the different waveform according to the result of comparative. Update 27th January The problem has been solved!!!! Tanks to @artvvb I will share some experience here to help others. First, just like what @artvvb said you need change the size of heap and the default value is just 2000, if you hope to initialise the ADC and DAC at the same time. Secondly, don't forget to use static to avoid the duplicate initialisation in loop, or the heap will overflow again. By the way, in my code, I enable two I2C, so the I2C base address of ADC and ADC are different. If you use the default demo from the GitHub, please follow the answer from @artvvb.
  3. Hello friends, I am working on Eclypse Z7 with ADC ZMOD1410, I have performed acquisition of the signals as per my requirement. I am using two ZMOD’s with four channels for acquisition of signals. However, I need clarity on output format of channel 2(or B) of each ZMOD’s, whether it is in 2’s complement form or gray code format. When checked into the VHDL code of ZMOD low level controller 1410 IP, the ADC SPI command is x"001421" which is written for 2’s complement and followed by x"000502" means device index B and that can be verified with datasheet. But at the same time, in the comment it is mentioned that channel 2(or B) is having gray code as output format. I applied same signal to both channel 1 (or A) and channel 2 (or B) of same ZMOD, if I consider the output format to be 2’complement for both channels, I expect nearly the same the data. However, this is not the case, channel 2 (or B) is having different values. Whatever constant DC voltage applied to channel 2(or B) is treated as zero level when plot the digitized data. If anyone knows any information about the same, it’ll be very helpful. Thanking you in advance.
  4. Hello, We have been developing a real time data transfer application using Genesys ZU-3EG boards along with Zmod DAC/ADC pair. We previously built the application on Eclypse boards and now are migrating the design to Genesys boards. In the process, we have discovered that one of the two Genesys boards is failing to power up the DAC and ADC pods regardless of the fact that our designs are running exactly the same initialization protocols for both of them. We have verified this by inserting both the DAC and ADC pods to both Genesys boards and running some tests. On one board (board A), both DAC and ADC pods prove to be working. For DAC, this is verified by seeing DAC output on Oscilloscope when running our TX design, and for ADC, this is verified by giving an external signal to ADC and observing ILA outputs while running our RX design. On the other board (board B), ADC output appears to remain constant as seen in the ILA regardless of whichever signal we provide through the signal generator. Additionally, DAC's low-level controller IP in Vivado has an init_done_n signal which goes low after it is initialized. In the case of the working board (A), we see this signal going low, and the DAC works, but in the case of the non-working board (B), this signal remains high, meaning the DAC configuration is not done, and we don't see any signal at the DAC output. Observing this init_done_n not going low on the DAC in board B actually made us realize the problem after which we ran these additional tests for verification. All jumpers settings of both boards are the same. We are using jtag mode for programming the PL. Finally, it is to be noted that PL and PS are working okay on board B. It's just the DAC and ADC pods that are not responding. What do you believe is the problem? Are we facing a production based error on SYZYGY connector on board B? Any suggestions on how to proceed? Thanks, Nasir
  5. Hello, I am currently developing a project with the ZmodADC1410_Demo_Baremetal of Eclypse-z7. The development environment is vivado 2019.1. I use the lwip software protocol stack in the SDK, RAW API mode, and I want to use UDP through the Ethernet port on the PS side. Send the adc data to the PC (only the data of channel 1), I have now completed the spectrum analysis of the collected data on the PL side based on the adc demo, and then sent the data to the sCH1in [13:0 ] Port of the ZmodADC1410AxiAdapter IP, now I have encountered difficulties in writing the PS-side program. I am confused about how to combine the adc data sent by udp and the adc demo. Is there any relevant example for reference? If not, I hope Digilent can develop a demo for Eclypse-z7 to send adc data via udp. Thank you to anyone that can help!
  6. I am in the proposal process that utilizes the Eclypse Z7 along with the Zmod ADC 1410. We are hoping to utilize vetted code to configure the ADC and accept the sample data. We need to do some processing and interfacing to external components so we cannot use the provided bit file. I have looked over GitHub repository (https://github.com/Digilent/Eclypse-Z7-HW) and couldn’t find any VHDL or Verilog files?