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digiuser1970

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  1.    digiuser1970 reacted to an answer to a question: Vivado MIG corrupted reads in 2:1 mode
  2. digiuser1970 started following MIG project for ARTY 100 , Using DDR as a Video Frame Buffer , A Guide to Using DDR in the all HDL Design Flow and 1 other
  3. digiuser1970
    What I am missing is a mig project file. I would expect the "mig_a.prj" and / or information how to configure the MIG to get the design complete. (?)
  4.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  5. digiuser1970
    I can second several issues with the MIG as mentioned of the pages before. I recommend to go with a standard routing provided by the MIG which has the highest reliability to work. Thanks Zygot for your work. Very informative!
  6.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  7.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  8.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  9.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  10.    digiuser1970 reacted to a post in a topic: A Guide to Using DDR in the all HDL Design Flow
  11. digiuser1970
    Generally these mismatches regarding voltage settings can be caused by a default voltage setting which is applied for pins which are not explicitely constrained. Not sure if this is the error here. A question of mine: Where did you derive this XDC from? It seems to be the MIG's output. How did you setup the MIG to be sure to adapt to the wiring Digilent applied at the PCB?
  12. digiuser1970
    Where is the announced MIG project for ARTY 100? The reference manual https://digilent.com/reference/programmable-logic/arty-a7/reference-manual says: The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Arty A7 Resource Center to speed up this process. It is included in the “MIG Project” design resource download. This download also includes a .prj file that can be imported into the wizard to automatically configure it with the options found in Table 2. Now, where is it? We urgently need to evaluate a DDR-Design for an ARTIX 100 to decide whether to go with Xilinx A7 or not. Alternatively you may want to complete the table in the docs with a complete description of the bank setting to be done in the MIG in order to obtain the wiring you are using, or at least upload this xdc. Thanks.
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