Jump to content

Search the Community

Showing results for tags 'genesys2'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 15 results

  1. I just bought a Genesys2 board recently. Only the Vivado ML Enterprise Edition license is allowed to use Genesys2 board (The free Vivado ML Standard Edition License can not see the Genesys2 board at all). However, the Vivado ML Enterprise Edition license unlocked by the Genesys2 voucher will expire in 30 days (not permanent). That means I HAVE TO pay extra money( $2995 for a Node License, $3595 for a floating license) to continue the Vivado Enterprise Edition license after 30 days to use the Genesys2 board for any future development. This is not mentioned in any Genesys2 product shop/reference link web pages. Is this fair to the users of Digilent Genesys2 product?
  2. I am working with a custom-made FMC (HPC) that attaches to a Genesys2 board with VADJ=3.3V. Among various signals, I have two LVDS_25 clock inputs on the pairs L25/K25 (FMC pins K4/K5) and F12/E13 (FMC pins K28/K29): set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVDS_25} [get_ports clk0_p]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2] set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVDS_25} [get_ports clk0_n]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2] create_clock -period 9.523 -name clk0_105mhz [get_ports clk0_p]; set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS_25} [get_ports clk1_p]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06] set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS_25} [get_ports clk1_n]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06] create_clock -period 9.523 -name clk1_105mhz [get_ports clk1_p]; To my understanding, both pin pairs are clock-capable and Vivado synthesizes/implements without issues. The HB bank is powered by an external voltage of 3.3V from the FMC card. For sanity checking, I pass both clocks through IBUFGDSs... wire w_clk0_ibufg; IBUFGDS clk0_ibufgds_inst (.I(clk0_p), .IB(clk0_n), .O(w_clk0_ibufg)); wire w_clk1_ibufg; IBUFGDS clk1_ibufgds_inst (.I(clk1_p), .IB(clk1_n), .O(w_clk1_ibufg)); ...divide the clock and power a couple of LEDs to confirm signal availability: reg [25:0] r_clk0div = 0; reg [25:0] r_clk1div = 0; assign led[0] = r_clk0div[25]; assign led[1] = r_clk1div[25]; always @(posedge w_clk0_ibufg) begin r_clk0div <= r_clk0div + 1; end always @(posedge w_clk1_ibufg) begin r_clk1div <= r_clk1div + 1; end To my surprise, I see only led[0] blinking (with irregularities), but not led[1]. I see a LVDS signal on the FMC connector pins of both clock inputs. The signals are somewhat distorted (oscilloscope struggles to trigger at the proper period) and led[0] blinks irregularly at times. Due to reasons, the FMC is connected to the Genesys2 board by an 250mm cable [1]. My guess is that the additional connector introduces reflections and the cable attenuates the clock signals to a degree that the FPGA does not detect a LVDS signal. Is it really this "simple", or am I missing something? [1] https://www.mouser.ca/ProductDetail/200-HDR-169468-01
  3. I have a Genesys 2 board and I am trying to program the FPGA with the SD card but the PIC stopped working that controls the SD card programming. I have a pickit4 and pickit3 to reprogram it, but I don't have a hex file to program it with. Would you be willing to send me that file?
  4. Hi guys, I bought my genesys 2 last october, and now when I turn it on, the out of box demo would only succeeds a fraction of the time. More over, previously verified bitstream would only work once after programming with jtag several times. I suspect the fpga chip is a defect. How do I use my warranty? Thanks
  5. I using Genesys2 boards. I can see that the package have "CE" note, but i can not find any documentation about it. As i undderstand it, one of the manuals had to contain a reference to directives and product standards. Where can i got a "Declaration of conformity" ?
  6. Hi, I am very new at field of FPGA. Now I am working Genesys2. I have to control DDR3 memory. I find some examples in Digilent site for DDR3 using microblaze processor. But, in my case I don't have to use microblaze processor. I have to send some fixed value through the DDR3 memory like 8-bit data (X'FF') i.e. I will write that data into the Genesys2 DDR3 memory and readout the data from the memory. I already go through Xilinx manual ug_586 . But still it is not clear to me how to start coding for the DDR3 memory. My questions are: 1) Is it possible to have example code without using microblaze processor for DDR3 memory? Or any suggestion for starting code to control DDR3 memory. Actually, I have do it in any way. So any helpful suggestion will be appreciated. Thank you.
  7. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  8. Hi, I have a RISC-V design implemented on the Genesys2, with a UART that currently works through the USB-UART microUSB port, which just uses the uart_rx and uart_tx lines. I would like to send the UART output through the PmodBT2 to my Mac instead (connect via "screen" command in a terminal). From the Nexys 3 FPGA reference design, I believe I should connect the my uart_tx port to RXD pin on the PmodBT2, and uart_rx to TXD. I have done this and programmed the FPGA, and also established a connection to PmodBT2 from my Mac. However, when I run a hello world, I don't see any output in my terminal window. Do I need to do anything with the additional pins on the PmodBT2 (CTS, RTS, RST, STATUS), or change any settings on the PmodBT2 from the default? The Nexys3 FPGA reference design appears to set RST to 0 and CTS to 1--I tried this but did not see any change. I only want to send data from the Genesys2 to my Mac (one way traffic). Any help would be appreciated. Hugh
  9. Hello, Could you please elaborate on this: "... for a limited time a voucher with Design Edition will be included with no additional cost." Is this licence time limited in any way, I.E. will I have to purchase a DE licence at some point in the future or will I be able to use the current version with this board forever? Is the voucher valid for a full licence or just a discount? Another question, if I purchase a Digilent board through a 3rd party reseller like Mouser electronics, do I still get the voucher? Thanks! regards, Vedran
  10. Hi, I'm a newbie trying to learn about the Genesys 2 board and would like to program the onboard OLED as an exercise. I'm following this tutorial. There is a prominent warning that says "Important! Make sure to turn off the OLED display before shutting down or reprogramming your board." Why? What will happen if I don't turn off the OLED display and simply turn off the power switch? Will it get damaged? This makes me very nervous to try my own programs since I will probably mess up at some point. Can someone reassure me that I won't do any permanent damage? Thanks!
  11. Hi everyone i am using genesys2 board. I want to test the board with simple code. but i meet a problem with clock, can you help me to fix it? thank this is code: and this is xdc the error in bitstream like this [DRC NSTD-1] Unspecified I/O Standard: 1 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk.
  12. Hello, I'm designing a custom FMC board to use with my Genesys 2. Is there any informations about GTX and serdes pair length ? Thanks
  13. I need to use the IBERT IP core on a Genesys-2 FPGA board. I am using FMC-SMA board to convert FMC into SMA. In the clock settings I am using the external clock source from pin AD-11/12 of 200MHz. But the problem is I am unable to get any output as PLLs are not locked. I had followed the same steps with FMC board and all things where working fine. 1. Can I use the internal clock in the clock setting. (I tried but getting the INFO:- [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. ) 2. Do I need a clock source on FMC-SMA board, as the place holder is provided but the oscillator is not provided by default.
  14. Hello! I am working on implementing the IBERT IP core on the Genesys2 dev board. I have purchased this daughter board to connect to the FMC, but I am unsure of how the pins relate to the SMA connectors. Has anyone used this daughter board before? I have emailed Hitech Global for documentation, but I have not received a response as of yet. Also, does anyone know if a guide such as this one exists for the Genesys2 board? I assume that the steps would be very similar since they both use the Kintex-7 FPGA. Thanks
  15. Just received a new Genesys 2 board. Flashed it and trying to boot the prebuilt version of linux from arian-sdk Programmed the board according to here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-programming-guide/start The board powers up fine, copies bbl & linux image from sdcard and then no tty output. Nothing at all. I built the sdcard using the prebuilt bbl.bin images from: https://github.com/pulp-platform/ariane-sdk/releases (I tried bbl.bin files from both 4.2 release and OpenPiton + 4.2, same result for both.) Following instructions for creating sdcard here: https://github.com/pulp-platform/ariane-sdk Board sees the sdcard, copies the sectors, and then nothing! I've tried to set breakpoints at numerous places in the linux boot sequence but non of the are ever hit. Breaking in from gdb shows $pc at 0x10040 which seems wrong for linux running at 0x80000000. Main questions are: Are the prebuilt bbl.bin images known to work? Are instructions up to date? Any suggestions on how to move forward? Thank you! Uart output is below. I expected to see some linux boot lines following the 'done!' message below but I get nothing. Hello World! init SPI status: 0x0000000000000025 status: 0x0000000000000025 SPI initialized! initializing SD... SD command cmd0 response : 01 SD command cmd55 response : 01 ... SD command cmd41 response : 00 sd initialized! gpt partition table header: signature: 5452415020494645 revision: 00010000 size: 0000005C crc_header: 321D0047 reserved: 00000000 current lba: 0000000000000001 backup lda: 0000000003B723FF partition entries lba: 0000000000000002 number partition entries: 00000080 size partition entries: 00000080 gpt partition entry 00 partition type guid: D5F7127456A1134B81DC867174929325 partition guid: 7123B019FB971546B5847A236525E8D9 first lba: 0000000000000800 last lba: 00000000000107FF attributes: 0000000000000000 name: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 gpt partition entry 01 partition type guid: AF3DC60F838472478E793D69D8477DE4 partition guid: 77C2133C1B594546B2902DC840F4A5C8 first lba: 0000000000010800 last lba: 0000000003B723DE attributes: 0000000000000000 name: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 gpt partition entry 02 partition type guid: 00000000000000000000000000000000 partition guid: 00000000000000000000000000000000 first lba: 0000000000000000 last lba: 0000000000000000 attributes: 0000000000000000 name: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 gpt partition entry 03 partition type guid: 00000000000000000000000000000000 partition guid: 00000000000000000000000000000000 first lba: 0000000000000000 last lba: 0000000000000000 attributes: 0000000000000000 name: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 copying boot image ................................ done!
  • Create New...