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Found 6 results

  1. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  2. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  3. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start https://projects.digilentinc.com/arthur-brown/displaying-color-readings-with-the-pmod-color-and-python-ebd794 and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c
  4. Hey All, I am trying to make a simple IP block design in Vivado 2018.3 to test the ESP32 PMOD out using AT commands for data transmission. I will attach a picture of my current block diagram to this post. I am getting a critical error (reference below) that says the IP has a packaged board value of "digilentinc.com:cora-z7-10:part0:1.0" which is for the Zybo z7 board. My questions are: Q1)Will this design work regardless of this error, as the Zybo and Zed boards are similar and both run off the zynq-7 architecture? Q2)If the answer to Q1 is "no", is there a method of adapting this IP for the Zedboard? (I should be using the latest IP library from Digilent) [IP_Flow 19-4965] IP PmodESP32_axi_gpio_0_0 was packaged with board value 'digilentinc.com:cora-z7-10:part0:1.0'. Current project's board value is 'digilentinc.com:zedboard:part0:1.0'. Please update the project settings to match the packaged IP.
  5. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  6. Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also involved setting up a clock backbone route in my constraint file. Instantiation: I've been instantiating my MIG with inputs set to 0 (except clocks) and outputs left open, just trying to get that init_calib_complete signal to go high. clk1 : clk_wiz_0 port map ( -- Clock out ports clk_out1 => clk_ref, -- Status and control signals resetn => reset_n, -- Clock in ports clk_in1 => sys_clk_ibufg); u_mig_7 : mig_7 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => (others => '0'), app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => open, app_rd_data_valid => open, app_rdy => open, app_wdf_rdy => open, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => open, ui_clk_sync_rst => open, -- System Clock Ports sys_clk_i => sys_clk_ibufg, -- Reference Clock Ports clk_ref_i => clk_ref, sys_rst => reset_n ); Constraints: I have one user constraint file bringing in the 100MHz clock from the board as well as buttons, switches, leds, and the audio codec signals for debugging and other functionality. It's attached to this post. MIG setup wizard settings: If anyone has experience with using this MIG or any clocking expertise, please let me know. I've been banging my head against this just hoping for a calibration, and I would really appreciate your help. Thank you!
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