On-board Flash/EEPROM memory in the FPGA

[Niranjana]

Hi,

I'm using Zybo Z7020 board (https://digilent.com/reference/programmable-logic/zybo-z7/start)

I'm trying to establish I2C communication from the Zynq to on board EEPROM of the device. When I referred the technical manual from digilent, I happen to find nowhere regarding the presence of on board EEPROM. Is there any onboard EEPROM/flash in the board?

Will be glad if you could clarify this.

[artvvb]

Hi @Niranjana

Please review the section of the reference manual on QSPI flash: https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual#quad-spi_flash

This memory can be used both for boot and for user data.

Thanks,

Arthur

[Niranjana]

Thanks @artvvb, 

I'm trying to establish a PS- PL communication thru i2c...for which I'm using an example reference code given in the Vitis SDK.

(xiic_low_level_eeprom_example.c) so is it possible?

Also, I wanted to know if there's any particular slave address for the same? I went thru the user's guide of the board but I'm unable to find the slave address!

I wanted to confirm whether my Block design is functionally correct (in Vivado)

Edited October 3, 2023 by Niranjana

[artvvb]

It looks like HDMI DDC interfaces use one of a couple of different fixed slave addresses, depending on the version of the standard that the particular display implements: https://en.wikipedia.org/wiki/Display_Data_Channel.

The block design is likely functional, but I'd need some configuration settings from the IIC IP and maybe Zynq PS to confirm. Constraints also matter, presumably the DDC interface is connected to the correct pins on the HDMI source/TX port. If possible, archiving the entire Vivado project would be ideal. See the attached screenshot

That particular IIC software example writes to an EEPROM and reads back to verify. You definitely don't want to be writing to the monitor's EDID. Look for something that only reads.

Thanks,

Arthur

[artvvb]

Oh - that's the HDMI input DDC, not the output. If using that connection, the AXI IIC needs to act as an I2C slave that can provide EDID information to computers connecting to the board, instead of as a master on the bus. Please confirm what physical connection you are trying to make between the board and the outside world.

Thanks,

Arthur

[Niranjana]

Hi @artvvb, Thanks for the quick response.

Quote

Please confirm what physical connection you are trying to make between the board and the outside world.

There is no external connection for the board. As the EEPROM is within the FPGA , I tried to run the example code.
You're right, I don't wanna write into the the monitor screen.

I am not sure about how to keep the EEPROM as output in configurations. Also its respective slave address is unidentifiable.
And When I referred : https://support.xilinx.com/s/question/0D52E00006hpQI4SAM/i2c-ip-connections-in-ip-integrator?language=en_US

I followed the same to keep PS as Master and AXI -PL as Slave.

 

12 hours ago, artvvb said:

You definitely don't want to be writing to the monitor's EDID. Look for something that only reads.

 

i2c.xpr

[Niranjana]

Adding to that, I am confused with these settings and configurations of Zynq PS:

The I2C1 is configured as EMIO..

But I didn't make any connections with respect to PS-PL IPs...Should I connect them as shown in the below diagram?

 

Edited October 4, 2023 by Niranjana

[artvvb]

These connections look plausible for a PS-PS loopback, but the AXI IIC is fundamentally a peripheral of the processor, and the processor is still controlling it. How is your EEPROM instantiated in the FPGA, would it be controlling the AXI IIC S_AXI interface? At that point, it would just be easier to implement an AXI slave that the processor can use to read data from the EEPROM. The EEPROM ought to either be written in HDL and added as an RTL module, or encapsulated in an IP. It could have an I2C interface and connect to IIC_1 on the PS block, but it needs to be represented in the project first.

[Niranjana]

14 hours ago, artvvb said:

How is your EEPROM instantiated in the FPGA, would it be controlling the AXI IIC S_AXI interface?

I'm using on board EEPROM(which is present in the FPGA itself). Yes, I realised that I've not instantiated any IP/ module related to EEPROM in the Block design which needs to be connected as slave to the PS IIC_1. I'm not sure on how to instantiate the EEPROM!

2.Even if I do , there is no slave address mentioned for the IIC EEPROM. In the Vitis SDK's given example code , they have mentioned reg. the slave addresses:https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/iic/examples/xiic_low_level_eeprom_example.c#L351

So can the user give their own 7 bit slave address?

Edited October 5, 2023 by Niranjana

[Niranjana]

I don't think this type of communication is possible. Because the EEPROM am trying to access is based on Quad-SPI Interface, but am trying to access via I2C interface.
I might need to use an external EEPROM chip which supports I2C:Example- https://www.electronicscomp.com/at24c256-i2c-interface-eeprom-memory-module?gclid=Cj0KCQjwmvSoBhDOARIsAK6aV7hn7EnbanQaLghuTKA4WcMn3d8TjgbbJyFyM1AOmvgD1CuA3OgkCukaAvZ9EALw_wcB

By connecting this to the PL side of FPGA , I can read and write data from PS.

Correct me if I'm wrong!

 

 

[artvvb]

Yep, the Zybo Z7 doesn't have an I2C EEPROM, inside the FPGA chip or otherwise. If you want EEPROM functionality that isn't based on I2C, look at the QSPI flash. If you need it to be I2C, look for external modules you can connect.