aleib_borgwarner

@zygot Yes, you described my experience so far; finding basic information has proved time consuming and confusing (I had thought that was just because I was new to this stuff and didn't know where to look). However, Once I had a grasp on Vivado and Vitis I could turn out experiments fairly quickly on the board itself. Plus the support from this forum has been absolutely great! I believe once you know where to look, you can find the information you need, but otherwise it is hidden behind very technical documentation. As far as performance, the board is very quick, at least with regard to the FPGA and Zmod Scope/AWG. We are doing Real Time Analysis/Digital Signal Processing and it holds up great, at least within the audio frequency range (20-20kHZ). I will take a look at that tutorial as that is essentially all we need from the PS, thanks so much!

Great stuff @artvvb, it helped to confirm some of my theories for controlling the PL from the PS, thank you! The method I've been looking at most heavily is around AXI. Now, I decided to do a custom AXI Controller since I had built another AXI interface for this project already, however, I can't figure out how to write values to the AXI stream from the Zynq processor. I'm assuming you can do all the writing to the AXI stream using a C script in Vitis after exporting the Vivado HW design, but don't know how to talk to the specific AXI ports I need. Hopefully that makes sense. Thanks again for the quick response!

Objective: I'm looking to control the values of specific ports of a custom Vivado IP module through an Eclypse Z7 board. Issue: I do not know how to "talk" to the FPGA after the initial programming of it, resulting in hardcoded values stuck on those ports. Additional info: From my research, I believe I would be able to generate a C/C++ wrapper of my Vivado project using Vitis, and then access certain ports through variables autogenerated within that Vitis project environment. But, I can't seem to find a way to decipher which variables/ports go where in relation to my Vivado project. Side note: It would also be nice to program the FPGA "permanently" so that when power cycled, it runs whatever VHDL and C scripts that were last programmed on it without requiring to reprogram the device every time through Vivado/Vitis. Thanks in advance! aleib HW/SW: - Vivado/Vitis 2022.2 - Eclypse Z7 w/ Zmods AWG and Scope

I agree. Thanks for the additional recommendation. Unfortunately, this project was picked up after the decision to use the Eclypse platform, so for right now we are more or less stuck with that decision, at least for an MVP. Definitely learning its limitations and such though. Thanks again for the resources!

Hey @artvvb Thank you for the quick response and pointing me in the right direction! I will take a look at the "low-level filter demo" and start moving my efforts towards redesigning the HW; I didn't realize the limited access I had with a SW approach. Will keep you posted if there's anything else I have questions about! Thanks again!

I am working on a SW project for BorgWarner using the Eclypse Z7 board along with the Zmod Scope/ADC and AWG/DAC. I got the demo projects working on the device and have made some edits using the Vitis IDE and the provided wrapper that came with the demo projects. However, I'm having trouble getting the ADC and DAC to "talk" with each other... ## The goal: Have an input signal to the ADC -> send signal to DAC in near-real-time. And maybe do some signal modulation in between. I would like to accomplish this within Vitis using the C/C++ wrapper provided with the demos, but if that is not possible, am open to other methods for accomplishing this goal