Handling User Inputs on Eclypse Z7

[aleib_borgwarner]

Objective:

I'm looking to control the values of specific ports of a custom Vivado IP module through an Eclypse Z7 board.

 

Issue:

I do not know how to "talk" to the FPGA after the initial programming of it, resulting in hardcoded values stuck on those ports. 

 

Additional info:

From my research, I believe I would be able to generate a C/C++ wrapper of my Vivado project using Vitis, and then access certain ports through variables autogenerated within that Vitis project environment. But, I can't seem to find a way to decipher which variables/ports go where in relation to my Vivado project.

 

Side note:

It would also be nice to program the FPGA "permanently" so that when power cycled, it runs whatever VHDL and C scripts that were last programmed on it without requiring to reprogram the device every time through Vivado/Vitis.

 

Thanks in advance!

aleib

 

HW/SW:

- Vivado/Vitis 2022.2

- Eclypse Z7 w/ Zmods AWG and Scope

Edited August 2, 2023 by aleib_borgwarner
Added HW/SW used

[artvvb]

Hi @aleib_borgwarner

There are a bunch of ways to control the ports of a custom RTL module from Zynq PS. The topic in general is communication between Zynq PS and PL (FPGA fabric). What approach you pick heavily depends on the requirements of the interface you want to control. How often you need to provide new values every clock cycle and whether values need to be provided even when the processor is busy doing other things are both relevant.

A couple of options to look into, in roughly ascending order of complexity/difficulty:
1. AXI GPIO
2. "Hard" PS peripherals like GPIO connected to fabric through EMIO.
3. AXI stream FIFOs
4. A custom AXI controller
5. DMA

You could also connect ports to external hardware, potentially via the Pmod port.

As for permanent programming, the board can be booted from flash or an SD card - see this guide: https://digilent.com/reference/programmable-logic/guides/zynq-baremetal-boot

Thanks,

Arthur

[aleib_borgwarner]

Great stuff @artvvb, it helped to confirm some of my theories for controlling the PL from the PS, thank you!

The method I've been looking at most heavily is around AXI. Now, I decided to do a custom AXI Controller since I had built another AXI interface for this project already, however, I can't figure out how to write values to the AXI stream from the Zynq processor.

I'm assuming you can do all the writing to the AXI stream using a C script in Vitis after exporting the Vivado HW design, but don't know how to talk to the specific AXI ports I need. Hopefully that makes sense.

Thanks again for the quick response!

[artvvb]

For the C side of things, AXI peripherals all get mapped to specific memory addresses in Vivado. As long as you know the base addresses and register map, you can do reads/writes to an AXI controller's registers by just doing reads/writes to their memory addresses. This could be as simple as something "value = (*my_register_address);" for a read. In Xilinx drivers, this is usually abstracted away through a bunch of macros and an API, with some hardware-design-specific information (like base addresses) coming in through xparameters.h.

[zygot]

23 hours ago, aleib_borgwarner said:

I'm looking to control the values of specific ports of a custom Vivado IP module through an Eclypse Z7 board.

The sales blurb for the Eclypse-Z7 still says "The Eclypse Z7 is specifically designed to enable the rapid prototyping and development of embedded measurement systems.. reducing the time it takes for engineers and researchers to develop innovative and powerful new high-speed instrumentation, control, and measurement systems for edge-computing, medical, and communications applications."

Curious as to whether this describes your experience with the board and support so far. I haven't cloned the repositories in quite a while and an hour ago I find that just getting basic information, like how many contiguous ADC samples does the AXI controller support, has gotten a lot harder to find. Still looking by the way.

If your application mostly is implemented in your PL logic and you only need a simple, low speed way to write control registers and read status registers to control your design, the simplest way might be to use the spare PS UART, through the EMIO, to connect your software to your logic. The basic idea can be found in the tutorial: https://forum.digilent.com/topic/22512-manipulate-pl-logic-using-ps-registers/ It might not be appropriate for your requirements, but if it is the effort to get your design working might be a whole lot easier. It might be worth looking at.

 

Edited August 3, 2023 by zygot

[aleib_borgwarner]

@zygot Yes, you described my experience so far; finding basic information has proved time consuming and confusing (I had thought that was just because I was new to this stuff and didn't know where to look). 

However, Once I had a grasp on Vivado and Vitis I could turn out experiments fairly quickly on the board itself. Plus the support from this forum has been absolutely great! I believe once you know where to look, you can find the information you need, but otherwise it is hidden behind very technical documentation.

As far as performance, the board is very quick, at least with regard to the FPGA  and Zmod Scope/AWG. We are doing Real Time Analysis/Digital Signal Processing and it holds up great, at least within the audio frequency range (20-20kHZ). 

I will take a look at that tutorial as that is essentially all we need from the PS, thanks so much!