Abady

Does adding any of these interfaces to your project help? (Add it just like you added the IP) https://github.com/Digilent/vivado-library/tree/master/if

Are you trying to read and write to the uart on the USB port? If this was the case then you are probably won't need this IP, the USB probably is connected to the PS side in the of the FPGA (bank 501) If you are trying to use UART from the GPIOs, then you probably need to check your connection from the schematic, and also you should either use the bus connection or the wire connection (either uart_rtl or rx_0&tx_0, not both), I think this should make your UART work

I have a project where I read images from a sensor, write the images to RAM using Xilinx AXI VDMA IP, read these images to process it then write it to RAM again and finally I read the images and send them to a display. This simply is my project. My board is custom with Artix t100 csg324 chip and DDR3, I use Vivado 2018.1 on Ubuntu16.04 LTS Every thing was fine, but at some random point (after new generation), VDMAs started sending extra pixels for every line! My image resolution is 640x485, I configure it in C using MicroBlaze CPU, but instead of sending 640 pixels for every line, one VDMA is sending 641 pixels per line, and the other is sending 644 pixels per line! The number of pixels is consistent for every line, and it happened to me three times (I restarted the project three times), I am used to using VDMAs, and I did almost the same project on ZYNQ7000 but never face this issue, and when I start the project VDMAs are working well, but at some point project is broken! NOTE: No timing issues, I tried to fix them all, but this didn't affect the problem unfortunately . Does any one have any idea where I should look or what could lead to such behavior?