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Found 4 results

  1. Hello, I'm using "Mipi-csi2 rx subsys" on KC705 & 0V5640 with FMC Digilent adapter. I obtain data from d-phy (fig1) but I can't obtain TVALID signal from AXIS output. Mipi-csi2 rx subsys is set to decode YUV422 10 bit signal, on 2 Lanes with LaneRate to 280Mbps. I modify the Xilinx cfg_init tab from 0V5640.h and set register: {0x3034 || 0x1A} 10bit {0x300e || 0x45 } MIPI enable || Two lane mode {0x4800 || 0x14} [5]=0 Clock free running, [4]=1 Send line short packet, [3]=0 Use lane1 as default, [2]=1 MIPI bus LP11 when no packet; Default=0x04 {0x4300 || 0x30} Format Control (YUV) Edit: I read from ISR=0x00022882: bit2-ErrFrameSync VC0=1 | bit7-ErrFrameSync VC3=1 | bit11-ECC 2-bit error | bit13-SoT error detected bit17-StopState Q0 How to set 0V5640 register 0to obtain valid frame with YUV10bit config? Q1 Which condition are needed to generate tvalid on axis output? Q2 Is there register to set to generate axis transaction from "Mipi-csi2 rx subsys"? Regards.
  2. Hello Everyone, We have develop simple imaging system based on Nexys Video development board. We have interfaced Sensor with VGA/QVGA resolution using PMoD ports which provides Monochrome 14-bit data and we are sending this data on Ethernet using UDP packets on PC. We have designed our custom UDP protocol for sending data. Currently we are having Nexys Video board but as per data-sheet this USB port is used for storing programming file. Now we would like start development of similiar imaging system with USB output port. We are new to USB development on FPGA. Can you please share us how to proceed.? How to get started with USB design in Verilog? Is this possible on this board?
  3. Lumahajjar

    Nexys4 DDR Camera

    I am currently using a Nexys4 DDR to implement a project for my University The project requires a video camera what’s the best camera that goes with Nexys4 DDR ? In term of resolution and everything else thank you
  4. Hi all, I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able to make it work. But I want to buid the project using custom IP's. and I found this project: https://lauri.xn--vsandi-pxa.com/hdl/zynq/zybo-ov7670-to-vga.html I used the same (working) VHDL code, the same XDC file, the same setup, and followed his instructions, but for some reason, whenever I try to create custom IP's (with or without AXI), I can't make it work, and the monitor says "no signal". Can anyone please help to figure out what I'm doing wrong here? Thanks, Shlomi.