Riccardo

Ok I understand. At this point I have another question: is there any way I can modify the original code that is working on the FPGA in order to set up a continuous acquisition and manage it with waveforms?

Hello, I recently started to use Waveforms in order to have a simple user interface to communicate with my Digilent Eclypse z7. I'm using it with two adc zmod1410 and a pmod da3. At the moment I'm trying to perform a continuous acquisition of a variable time length signal (in the order of seconds) varying the acquisition frequency during the acquisition. Which is the minimum time delay between two acquisitions of the scope in "repeated" mode? Do you have any suggestion on how can I do with waveforms? I already managed to do it in a bare metal vhdl applications, but when it comes to make it easy to use from a PC I started to meet too many difficulties

Thank you all for your reply, this solved the critical warnings and allowed me to modify the IP

Hello everyone Is there someone who can help me with this problem? I'm going to modify the AXI_ZmodADC1410 IP to let it control two ADC 1410 controller. This is my idea to let only one core of my Eclypse z7 to to control both ADCs (until now I had to connect ADC and core in a one to one fashion) and let the other core to do all the elaborations and transportation to the PC. I started modifying the IP but the problem here is that I can not use the Bus interface of digilent, because I can not find it in the original IP Do you have any suggestion? Thank you very much for your help Have a nice day Riccardo

Thank you zygot for your answer, I had a look around but did not have much time in last days to figure out a solution. Anyway I just realized that the board could have something that can help me without the use of external modules or cables: the USB Micro-AB device. Is this something easy to setup? I see that through the Block diagram in Vivado the USBIND_0 is already mapped into the right FPGA MIOs. If I want to use it, do I only need to use the functions in xusbps.h? Maybe the answer is "you just have to try it and don't bother us with silly questions". What I wanted to know is only if this idea could work or I do not have to take even in consideration. Thank you very much Riccardo

Thank you zygot, I think I will go on with the USB TTL UART cable suggestion: Can this (https://it.farnell.com/ftdi/ttl-232r-3v3/cable-usb-to-ttl-level-serial/dp/1329311?gclid=EAIaIQobChMIqODF3r3v_AIVxY1oCR3wEgQVEAQYASABEgJ-kfD_BwE&mckv=_dc|pcrid||plid||kword||match||slid||product|1329311|pgrid||ptaid|&CMP=KNC-GIT-GEN-SHOPPING-PMAX-NCA-Short-title-test-21-Dec-22&gross_price=true) be ok for the application? I can use two of the pins available form PMOD ports of the Eclypse z7 and use them as TXD and RXD and then connect the ground, is it right? Or is it better a solution with an actual board like this https://ftdichip.com/wp-content/uploads/2020/07/DS_FT4232H_Mini_Module.pdf ?

Thank you zygot for your reply. I am actually using the Vitis serial terminal, which maximum baudrate I can choose is 115200, so maybe even only the 921600 baudrate you are referring can be faster, it the option for the baudrate in the SW code or is there any option to change in the platform.spr file of the hardware project? I will also look at the ethernet application. Do you know any example I can follow? Thank you for your time Riccardo

Hello I have designed a custom acquisition system with the Eclypse z7 modifying the example with the ADC ZMOD1410 https://digilent.com/reference/programmable-logic/eclypse-z7/demos/zmod-scope I managed to acquire a very large amount of data, which I want to transfer to the PC in some way. The method used until now is the uart connection (used as in the example) but it is very poor in speed and in order to transfer the whole acquisition (917448 samples) it takes about 30min! Is there any way in order to speed up the data transfer? I thought about ethernet connection but it seems very difficult to setup for me (I'm a beginner), in addiction I tried to settle up the echo server like in the following forum post but it did not work, as the image reported (Impossible to open a connection with the host n port 7: impossible to connect). Does anyone have a suggestion or an example from where I can tap into?

Hello Udayan, I tried to follow your tutorial on how to setup the ethernet port, but I am not able to ping that address with my laptop. Currently I am using an USB-ethernet adapter because my laptop do not have an ethernet port, but I'm quite sure that it is not representing a problem since I used even in other projects. Is the procedure valid for every PL that uses the Zynq block? I am using Vitis 2021.1 an this is the serial monitor: from this I understand that the ethernet link is settled, but it is not working. Do this happened to you while trying? Thank you in advance Riccardo

Hello Artur, sorry if I bother you I tried to open the project with vivado 2021.1, I migrated it following the procedure of vivado (updated all the IPs) with no modifications on the block diagram or constraints. When it comes time to open a vitis project, when I initially build the empty application (c++) project with the platform generated with the .xsa file coming from the exportation of the Hardware code I receive a makefile error: It seems like vitis can not generate the .elf file. Is there some warnings I have to sort out to be able to build the project?I can leave here the project in a zip file. I tried to do this because I have the same problem on another project I'm borrowing, which uses the same IPs. In the drive folder linked there are both projects: the first one named "hv", the second one (my project) "Adc_acq_system". https://drive.google.com/drive/folders/1OkhMl8JQ3Aqpc8SL3U86NzrDuaPovApL?usp=share_link Thank you for your time Riccardo

Hello Joe, sorry if I open this post again after lot of time. Did you manage to go into the all process without errors? Actually I'm stuck with a makefile error in combination with "ELF file does not exist". Does anyone know how to solve it?

Hi Antonio, I have a problem related to makefile now. The makefile is usually in "Vitis workspace folder"/"name of the project"_system/Debug. Since some time has passed, did you managed to solve the problem? Thank you Riccardo

Hello, I started to go through the customization of that block, in particular into the code for the circular buffer. I have a couple of questions: I don't understant why you initialized the dina and doutb as std_logic_vector(0 downto 0) instead of std_logic_vector(13 downto 0) Why is this process re-initializing all the control variables to '0' or "0" when it starts? I was finding a way to use both port of the Bram in order to read from port B while writing with port A. Is there any constraint you had to follow? I thoughted about creating a process in order to be sure to not read with portB from the same address where port A is writing and leaving the counter enable always active for both ports, do you see any criticity on this? Why are there some signals that are saved many times with R and RR? Is it only a mode to create a clock cycle duration pulse on xsOutAddrCntPulse (in this case)?

Hello artvvb. I'm trying to change the Hardware of the DDR streaming application. Every time I try to open the project this window appears: The problem remains even during the implementation. Is there somethin I did wrong? Currently Im using vivado2021.1. I tried to look for some solutions but it seemed that the only way is to reinstall vivado. In my project I removed the possibility to perform externally the calibration and the relays control, so now the interface for the ADC is the following (with all the control for trigger and son on..), so I'm not even using those ports. Thank you for your time Riccardo

Thank you artvvb! I managed to open it and I have a question: I saw many versions of the ADC ZMod IP, in particular the ZmodADC1410_Control and the ZmodScopeController. I saw that both of them are standalone in applications where no PS is used. I saw even the AXI adapter used in zmod adc-next to interface the ADC controller with the PS: that is the one IP that I hated when I was fighting against that buffer in the acquisition. Is there a way in order to override inside that IP or do I have to re-write that IP without that buffer? Thank you for your time Riccardo