zygot Posted December 15, 2021 Share Posted December 15, 2021 (edited) Think that you need AXI busses or complicated logic design to use the PL in your fancy ZYNQ device? Well, this demo proves that you don't. Find out how to read and write registers in your PL logic design just by reading and writing a few registers in the PS register set. By routing an unused PS UART to the PL via EMIO you can have a full-duplex data path as well as 6 additional input or output signals. What could be easier? EmioUartDemo_R1.zip Edited December 18, 2021 by zygot DougFPGA, JColvin and ohlala 3 Link to comment Share on other sites More sharing options...
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