Interfacing I2C sensor to PMOD. SCLK remains high (1) and unbale to receive the data on SDA

[gssr22]

Hello,

I am trying to interface BMP280 sensor (in I2C mode) to Ultrazed EG-IO Carrier card + SOM.

I connected BMP280 to one(JX1_JA_PMOD, 12pin) of 12 PMOD's available on the board.

SCL and SDA pins of BMP are connected to pin 3,4 of JX1_JA_PMOD.

I used AXI_IIC IP in vivado block design. Configured SCL frequency to 400 KHz in AXI_IIC IP.

Bitstream generation was succesful and exported to Vitis SDK.

Created a baremetal project on A-cores of Ultrascale+MPSoC (OS - standalone)

BMP280 address is 0x76 and its operating voltage is 3.3V.

Created an application to read the data in 0xD0 register of BMP280. I used the address offsets of AXI_IIC given in AXI_IIC 2.0 user guide.

When I degbugged SCl and SDA lines in Vivado, no clock signal is observed on SCL and no data on SDA line. Data read is always 0.

#include "xparameters.h"
#include "xil_exception.h"
#include "xtime_l.h"
#include "xstatus.h"
#include "xiic.h"
#include <unistd.h>
#include <xil_io.h>
 
#define XPAR_IIC_0_BASEADDR 0x80000000
 
int main(void)
{
 u32  i;
 u8  Buffer[255];
 xil_printf("\n--------IIC INIT------\n");
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x100, 0x1);
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x120, 0xF);
 
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x108, 0x1EC);
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x108, 0x0D0);
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x108, 0x1ED);
 Xil_Out32(XPAR_IIC_0_BASEADDR +0x108, 0x201);
 for (i = 0 ; i< 1;i++)
 {
   Buffer[i] = Xil_In32(XPAR_IIC_0_BASEADDR + 0x10C);  // Read data from RX FIFO
   usleep(15);
 }
 for (i = 0 ; i< 1;i++){xil_printf("mst rec 0x%0x\n\r", Buffer[i]);}
 return(0);
}

Here are my questions

1) I have attached screenshot of xdc file. Did I get the pin properties correct?
2) What is the reason that I can't observe SCL freq of 400 KHz when I debugged? Should I configure the SCLK frequency in Vitis?
3) Can I connect SCL and SDA of BMP280 to any PMOD GPIO pins? (except Vcc and Gnd)
4) Do I need to make changes to my code?

Vivado block design, xdc file, debugged waveform and axi_iic block properties are attached