Zmod Scope 1410 - Simulation Compilation Order Wrong, Cannot Correct it

[DeansOnTost]

Have a hair puller of a bug cropping up in my vivado project.

Trying to simulate a block design that uses the Zmod 1410 scope and Im getting the error of pkgzmodadc isnt in the xil_defaultlib.

dug a bit deeper and its looking like its compiling a file that uses the PkgZmodADC.vhd package file before it. 

Problem is I cant seem to move the file around in the compile, getting the error that its not in the simulation fileset even when the report_compile_order command is telling me so.

I'm hoping its just because its in the IP blocks filset and not the simulations directly but I'd take any advice before I go tinkering a bit too deep and brick my IP catalog

I am getting it to synthesize correctly though, just to add more confusion

I am new to the world of FPGA so might need  noddy answers

[zygot]

All files that are in the Vivado project hierarchy have attribute settings. Among those settings are ones that tell the tools if the file is for synthesis, simulation, or both. Not all HDL constructs can be synthesized. A good testbench usually has a lot of statements that are not supported for synthesis. That brings us to the point that in order to so a proper behavioral simulation, the toplevel entity must be a testbench file, and this must be marked as being used for simulation only. If you look in the project heirarchy view and right-click on any element listed there you can view all of the file properties.

Vivado ISIM is pretty good in most respects but not really easy to use as a general purpose logic simulator for proper a design flow. Proper design flow means creating a testbench for every entity in the hierarchy so that you can simulate all of it's parts independently from the bottom up. It is possible to add as many testbench files as you want into a VIvado project, but managing all of the simulation session possibilities is very unwieldy, unlike with a simulator like ModelSim.

Lastly, logic simulators like ISIM or ModeSim only support simulation of logic; so for a ZYNQ device this generally means that the tools are insufficient for simulating the whole PS/PL design.

Edited May 24, 2023 by zygot