DeansOnTost

Have a hair puller of a bug cropping up in my vivado project. Trying to simulate a block design that uses the Zmod 1410 scope and Im getting the error of pkgzmodadc isnt in the xil_defaultlib. dug a bit deeper and its looking like its compiling a file that uses the PkgZmodADC.vhd package file before it. Problem is I cant seem to move the file around in the compile, getting the error that its not in the simulation fileset even when the report_compile_order command is telling me so. I'm hoping its just because its in the IP blocks filset and not the simulations directly but I'd take any advice before I go tinkering a bit too deep and brick my IP catalog I am getting it to synthesize correctly though, just to add more confusion I am new to the world of FPGA so might need noddy answers