When I connect ui_addn_clk_0 to clk_ref_i I check that the clock frequency is 200MHz.
However when I run the synthesis I get the following error:
Quote
[Timing 38-469] The REFCLK pin of IDELAYCTRL sys_1_i/mig_7series_0/u_sys_1_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 5.275 ns (frequency 189.583 Mhz) but IDELAYE2 sys_1_i/mig_7series_0/u_sys_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
I noticed that the sys_1_i/mig_7series_0/u_sys_1_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200 is clocked off clk_ref_i which should be 200MHz according to the IP Integrator. However, if I use the "Clock Networks" report it indeed looks like the the 200MHz clock requested in the IP integrator is actually being generated as 189.583Mhz
Does someone know how to fix this? Should I just use another clock from outside the MIG? This seems to lead the critical timing errors during Synthesis and Implementation:
Question
Brenden
I was following the steps on https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi to play around with the DDR2 on the board. However, when I follow the steps I end up with a few Timing/Critical errors by default.
When I connect ui_addn_clk_0 to clk_ref_i I check that the clock frequency is 200MHz.
However when I run the synthesis I get the following error:
I noticed that the sys_1_i/mig_7series_0/u_sys_1_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200 is clocked off clk_ref_i which should be 200MHz according to the IP Integrator. However, if I use the "Clock Networks" report it indeed looks like the the 200MHz clock requested in the IP integrator is actually being generated as 189.583Mhz
Does someone know how to fix this? Should I just use another clock from outside the MIG? This seems to lead the critical timing errors during Synthesis and Implementation:
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