That doesn't make any sense. Try getting rid of RV core and see if problem persists, then you will know what the problem is.
You do know that each of GP ports has it's own address space, and attempting to access any addresses outside that space will never reach the port? See address map in UG585, Ch 4.1
Again, try getting rid of RV and see if problem persists.
Alternatively, you can use a debugger to inspect live transactions on AXI interface(s) to see what the heck is actually going on.
You did update the "range" column in address editor for a wider address window, right?
There is a trick to it which I actually used to tune trace length - if you select the trace in KiCAD, it will show you the current length of a trace in the status bar.
As for length tuning rules, I thought they are pretty clearly outlined in the MIG user guide. Here are the gist of them:
1. All traces are subdivided into length matching groups, and they only need to be matched inside the group, not neccessarily with other groups. Address and control signals (Axx and BAx lines, RAS/CAS/WE/CKE/ODT and CK/CK#) form a single group, and each byte lane (8 data lines, DQS/DQS# and DM) form a separate byte group.
2. Within each byte group traces need to be matched to 20 ps (so ±10 ps from reference length)
3. Address/control group need to be matched to 50 ps (±25 ps)
4. Address/control group need to be at least as long as the longest byte group.
5. Each differential pair (CK/CK#, DQSx/DQSx#) need to be matched to about 5 ps
6. Do your best to route each group the same way - using the same layers, same amount of vias, etc. If it's not possible, remember that a) signals on outer layers travel faster than on internal layers, and b) if vias are not used uniformly in a group then they add additional delays. This is why abovementioned rules are set in units of time as opposed to units of length. Most modern commercial eCAD tools can work with time units for matching as well as length units, so I highly recommend setting up rules in terms of time.
7. To help with routing, you can swap around pins for bit signals within each byte group, and address/control signals (again within the group). You can also swap around entire byte lane groups between each other (for example connect byte lane 0 of FPGA to DDR's byte lane 1 and vice versa). You can NOT swap lines from different groups, and you also can NOT swap positive and negative lines of differential pairs.
8. I used 50 Ohm impedance for single-ended signals and 100 Ohm differential impedance for differential pairs. MIG user guide specifies 50/100 Ohm for DDR2/DDR3 interfaces up to 533 Mhz, and 40/80 for higher frequencies.
Now, specifically for Spartan-7 and DDR2 the interface speed is going to be rather slow (depending on package and speed grade, it will be 333 or 400 MHz), so a lot of these rules can be somewhat relaxed. For example, in my project's PCB layout I forgot to take via Z-length into account during length matching, and the interface still works just fine. But the higher the frequency (this mostly applies to DDR3 which can go as fast as 933 MHz per JEDEC), the more strict those rules become, which is why I strive to obey them to the best of my abilities. Now, again in that project the goal was to make the project as affordable to build as possible, which is why I went for 4 layer PCB, but generally I highly recommend going for at least 6 layers, but preferably 8 because you can take full advantage of plane capacitance and route your high-speed traces on internal layers so improving EMI/EMC.
Finally, before you get on with layout at all, create a test design in Vivado to make sure the pinout you've chosen will actually work, and update the DDRx pinout to the one you actually have after all pin swapping once your complete layout to confirm the same. You can also use that design later to perform initial hardware checkout once you have the assembled board.
Good luck and let me know if your have any further questions.
If you install the board files for that board, there is a MIG project inside. if you go with the IPI, you can simply drag the DDR component onto the diagram, and it will set everything up. Or you can download a MIG project file in DIgilent's github repository: https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys2/H
The "8 series" is already out for many years - it's called "UltraScale" and built on 20nm process. Their "9 series" is also out - called "UltraScale+" and built on 16nm process.
