Yizakat

The & (ampersand) tells the command shell to execute the command asynchronously, that is, it will return immediately to the command prompt after starting the executable. Without the &, the shell will be blocked from executing other commands until you end the application. Essentially 'run command as background task''.

You can start the application from a terminal window. The executable is waveforms and should be located somewhere on your path. Mine is in /usr/bin on Unbuntu. You can create a Gnome launcher for it if you prefer to use the desktop menus.

I think this is exactly the problem. I encountered this same issue and worked through the HDL to come up with the same calculations as the OP. The tutorial/example loops the ui_addn_clk_0 back as the clk_ref_i for the Mig. This, as you say, is Mig output driving Mig infrastructure. The clock-divider can't be tweaked to hit 200MHz although it can get pretty close. The example project download provided by John exhibits exactly the issue being raised (at least, for me, in my Vivado 2022.2), plus a few other timing problems. Perhaps these don't impact the functionality of this simple design but I find them hard to ignore. Like the OP, I provided a 200MHz stable clock to clk_ref_i to address the REFCLK critical warnings (which corrects the negative TPWS). The negative slack can be corrected by driving other IPs (AXI etc) using the slowest ui_clk (81MHz). Perhaps some targeted pipe-lining might be better but since DDR2 speed is a limiting factor for me, this is not a problem so I haven't dug any further. There is probably a better solution. Resulting in:

Hi, TLDR; The Nexys A7 board file needed to be updated from 1.0 to 1.2. Vivado version is 2021.2. I'm using the Nexys A7 100T. The board file version was 1.0 That caused the problem, I didn't notice that I'd not updated the files in <vivado>/2021.2/data/board/board_files when I pulled the latest from your GitHub repo. Having update these files the board file 1.2 is now being used and things are much better. On the plus side, messing with the IP and trying different things, tweaking timings and building the Audio DMA demo to try and establish what is different and why that works has all cemented this firmly in my head so that is of some value! Thanks for your time on this. Y.

Good Morning Folks! And it is indeed morning, it has been a long day, I started this journey yesterday morning. By way of introduction, and to set an expectation of my level of understanding, I'm an embedded software engineer just dipping a toe in the waters of FPGAs. So very new to this! After a few weeks of playing around with the Verilog and RTL I'm now interested in Microblaze and following (faithfully or perhaps more accurately blindly) the guidance in https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi Sadly, things have not gone as smoothly as I had hoped. Despite sticking closely to the guidance I keep ending up with the following warning, which ultimately leads to a routing error: [DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell processor_i/mig_7series_0/u_processor_mig_7series_0_2_mig/u_ddr2_infrastructure/gen_ui_extra_clocks.mmcm_i. The computed FVCO is 562.500 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 15.000, CLKIN1_PERIOD = 26.66667, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)). I'm using a Nexys 7-100T so substituting DDR2 where the guide refers to DDR3, otherwise it is all pretty much identical. I have the constraints file is in place and the vivado board file is also correct. The system clock is correctly named and uncommented. This is, of course, all generated by the various automated connection and block assistants, I barely had to do anything manually. Having researched this there are a fair number of reports of this but mostly seem to be related to older versions of Vivado or people not setting up Clocking Wizards correctly. The tutorial doesn't use a Clocking Wizard, instead relying on timing from the MIG IP and I'm using the current version of Vivado. I can see where these values are defined in the generated IP constraint files but I really don't think I should be in there changing stuff to make this work. One thing I have noted is that the MIG clock period is defaulted to 3333ps (approx 300MHz), I seem to recall that the reference guide for the board says 350MHz for DDR2 but the IP configurator won't let me go higher than the 300MHz, in any case the tutorial doesn't ask me to manually change anything so I've let that be what it is. Any pointers (in English rather than FPGAish) would be greatly appreciated. As for me, I'm going to bed and will face this again in the morning :-) Cheers, Y.