asmi

The only caveat being what you've said just above the quoted - just because you connect a device directly to a USB port of a motherboard, it doesn't mean that this is actually a root USB port and not merely one of ports from onboard USB hub. This is not so bad for USB 2.0 as most hub chipsets I've came across had no problems processing nearly full USB 2.0 bandwidth at line speed, but things get a lot dicier with USB 3.x hubs and multiple USB 3.x devices. But since USB 3.x hubs actually contain two separate hubs (one for USB 2.0 and below, and another one for USB 3.x), a USB 3.x device can coexist with USB 2.0 device(s) without any interference because these two standards use physically separate channels for communication (and two separate controllers inside chipset/port controller). Given the question in the OP - since UART doesn't come anywhere near saturating USB 2.0 bus, (infact it won't saturate even USB FS at 12 Mbps), I don't see the problem. Unfortunately there is another "but" - if you use some sort of UART over USB-JTAG adapter (like Digilent's HS2/HS3), there are known cases when they refuse to work when connected through certain hubs. I'm not entirely sure if it's a hardware problem or a software one (or a combination of two), but it does happen sometimes, and in this case user will need to connect those adapters directly to motherboard USB port.

You can simply reassign a MAC address on your new system to be the same as what you had in the old one, and license will work just fine. I've done it for my license which came with my Genesys 2 board when the time came to replace my PC.

I don't know - that's what debugging is for. I would begin with inspecting an AXI bus from that core in a debugger just to see what's going on there. Also the kind of syncronization you use is not the best - I would use a mutex or a spinlock with atomic operations on both sides, instead of constantly resetting the core. Ditto for using AXI GPIO to control internal signals - I would create a simple custom AXI-lite slave with a single register. Thought I know some people prefer using PS GPIO ports 2 and 3 via EMIO as they give up to 64 channels for zero logic cost (you wil probably need to resyncronize it in PL as PS GPIO is likely running on a different clock from whatever you've got in PL - but that of course is only important for syncronous signals).

Maybe you should stop for a second and actually read and attempt to understand what IDE is telling you? Specifically, you are trying to create a 128x131072 FIFO, which requires almost 17Mbit of BRAM, while your target device (Artix-7 A100T) only contains 4.8 Mbit. Hence the message - "you're requesting more BRAM blocks than your target device actually contain. Consider targeting a larger capacity part, or reduce your demands to something which your target device actually has".

That doesn't make any sense. Try getting rid of RV core and see if problem persists, then you will know what the problem is. You do know that each of GP ports has it's own address space, and attempting to access any addresses outside that space will never reach the port? See address map in UG585, Ch 4.1 Again, try getting rid of RV and see if problem persists. Alternatively, you can use a debugger to inspect live transactions on AXI interface(s) to see what the heck is actually going on. You did update the "range" column in address editor for a wider address window, right?

No need for any of it - you can simply change the address range in the address editor, and Vivado will figure out the rest by itself: If you have separate instruction and data buses (like it's shown in the screenshot), you will need to change it in both places.

If you are only after a license for a single chip, then sure, but if there is a chance that you might want to use some other "paid" devices as well (for example K355T have increased number of MGTs than K325T and so might be very appealing for certain designs), then it might be better in the long run to just pay up once and get access to ALL devices, which includes some very interesting US and US+ devices. That's for sure - at least you can still use the devboard you once bought at any time in the future.

I wish there would be more affordable way (as I've also stuck on old version of Vivado with my 325T board), but it looks like there are only two ways - either buy a new board with K325T part and a voucher, or buy a full license (it will give you access to all parts). Both of those are quite expensive.

I've designed a number of boards with Artix-7 and Spartan-7, and never bothered with power sequencing - I always ramp up and down all rails at the same time via "enable" signal of corresponding DC-DC converters, which is connected to a switch that acts as a power on/off switch for the board. The only downside of such design is that as long as the power supply is physically connected to a board, the "power in" rail (on my boards it's typically 12 or 15 V) is "live" even when the board is switched off via power switch, and it's something that should be kept in mind when tinkering with a board lest one accidentally shorts that rail onto something and bad things can happen.

It's a well-known fact that micro-USB connectors are not very reliable, so those customers who care about this should just stay away from products which use micro-USB. Incidentally I haven't ripped out a single micro-USB connector in my entire life, but I still moved all my new designs to USB-C because it's just more convenient to use. Your assertion is meaningless because nobody in their right mind will do two separate spins of the same board with different connectors. And since A7 board was designed at a time when USB-C wasn't a thing, their options were a (relatively) big and bulky TH mini-USB, or an SMT micro-USB (I don't even know if TH micro-USB connectors ever existed, much less at that time, because their chief value proposition was that they were smaller and so it takes less PCB area). Also A7 PCB is quite high-hech even by modern standards, consequently back then it was pretty much a bleeding edge, so it must've cost them a fortune to manufacture and assemble them all those years ago (even today placing 0201 and 01005 usually commands a premium). WIth that in mind saving PCB space wherever they can must have been a strong motivation. Why haven't they redesigned the board more recently to use modern connector is a good question, which probably comes down to cost as well - PCB engineer's time is very expensive, so their calculus probably was that it's not worth it.

Actually it saves quite a bit because TH parts are often soldered manually, and so you pay for each individual TH part that you have on a board. Which is why many manufacturers now experiment with reflowable TH parts. Thought most modern USB SMT connectors have semi-TH tabs which can be soldered via reflow for additional mechanical strength.

I meant what was you doing with it that caused USB port to be ripped out? That's gotta require some serious force. This devboard is designed to be used in a lab, as it doesn't even have mounting holes if my memory serves me. Devboards are supposed to be used for prototyping, before spinning out a custom board specific to your application, and that board is supposed to have proper mounting provisions (hole pattern, physical size & shape, etc.). Not sure what you used epoxy for.

OMG, what the heck were you doing with that board?

If you need speed, FT60x is a very good option. On my custom board with FT601 I was able to reach about 2.5 Gbps of raw bandwidth (after all overheads are accounted for) over USB 3, and it's interface to FPGA is very simple (though it consumes a lot of IO pins). As far as I remember, FTDI also sells FMC daughterboards with those devices if you don't want to roll your own for some reason.

That new IDE is buggy as hell at the moment. At least for me. Good thing that they've kept the "classic" one so I can actually get things done.