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BASYS3 with Microblaze in Vivado 16.x


abcdef

Question

I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2.  I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works.  However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below.

My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2?

Here is some additional information, for anyone interested:

To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High.  Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x:

  Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;)    then File / Launch SDK.  In SDK, use File / New Application Project and select the Hello World application.  After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program.

As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze.  Strangely, the Microblaze design does not create any error messages or obvious warnings.  Greatly appreciate any insight. Thanks.

mb1.png

mb2.png

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Hi @neha,

What version of Vivado are you using? Could you also include a screen shot of your block design. I went through the getting started with Microblaze servers tutorial here in Vivado 2016.4 with no issue. I attached the project below. Vivado will connect your system reset to sys_rst on the MIG.  If you are using Vivado 2015 or below you need to make sure that you Connect this new reset port to the resetn input on the Clock Wizard block as described in the tutorial.

cheers,

Jon

Arty_echo.zip

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Hi @neha,

I unfortunately have not used Xilinx's fft IP. The Xilinx user guide for the IP is where we usually turn when looking on how to work with a specific IP. Here is the Fast Fourier
Transform v9.0 LogiCORE IP Product Guide. Here is a project that I believe uses the Xilinx fft IP with HDL. This might not be exactly what you are looking for since it is with HDL but it should show you what pins connect to what.

cheers,

Jon

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Thanks for your help but I finally made some progress and got it working.  : )  See the attached block diagram below.  To answer my question above, the Microblaze with an AXI peripheral does work on a BASYS3 board.

Two comments: 1) the main mistake with my original design was that the reset was set to active HI; it needs to be left active LO as shown below. 2) The hello program will only start once you have hit "reset", i.e., BTNC on the BASYS3 board. (This is some minor issue I still need to look into.)

Finally, I cannot stress that (at least for me) only the step-by-step approach outlined above worked with Vivado 16.x and SDK.  Maybe there are other ways to get it to work but the examples published for Vivado 15.x no longer worked.  If anyone is curious, I can post a more detailed description on how to implement the design.

abcdef...

mb3.png

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@jpeyron 

hi

I am implementing Ethernet server via above mention steps, but I am not using ddr3 for memory instead  that i am using flash memory.I am getting failed timing message with implementation complete .clock 1(166.667 mhz) of clocking wizard is connected exi_spi_clk, clock2(200 mhz ) with s_axi_aclk and clock 3(25 mhz )  as mentioned doc.
two processor reset create , 200 mhz processor  exi_reset and mb_debug_sys_reset is connected  with exi_reset and mb_debug_sys_reset of 166_reset processor respectively. aresetn of flash is connected with pheripheral arsetn of 200_processor_reset.

xdc file is shown in pic 1

latter i tried also make 4 port concat and connect  port 2 and port 3 to interrupt of uart and axi_quad_spi . I am able to generate bit stream too now, earlier bitstream was not generating. while launching sdk some  system.mss file is not generating

please guide me

pic1.png

pic2.png

pic3.png

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On 7/13/2016 at 4:44 AM, jpeyron said:

Hi abcdef,

I was able to get the microblaze "hello world" working for the Basys 3. Microblaze set to 128kb for local memory and no cache config.  I needed to add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1.  I am also making a Getting started with microblaze tutorial.

basys3_esc_2.jpg

basys3_esc_1.jpg

I am not able change ext reset logic level to 1 in my its 0 and its disable from click. what to do?

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Hi @neha,

You do not need to do the above process to get the hello world to work. At the time our board files were set up wrong for the reset and were fixed around the time period of the forum question you have posted on. If you recently installed the board files from here your design should work exactly like the tutorial here. Sorry for the inconvenience.

cheers,

Jon

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Hi @ jpeyron

 I am using vivado 2015.2.

thank you for making arty tutorial. I follow your tutorial  thoroughly, Implementation have lots error . The line You mention for .xdc file generating  a file of mig_7 series file. In order to remove error I made some changes.

1 I replaced all SPLIT with LVCMOS33

2. As per sch. I tried to change some pin

and in my version vivado in mig7 series to port of clk is coming 1 for 1 for n. ref and sys clk  npin i assigned with  external port.

 

errormsg.png

xdc.png

bd.png

mig_7.png

arty_sch.pdf

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@jpeyron

Greeting

Ok thank you,

But I  Have some question it is possible in this way or not(i mean using flash memory).

 

, As you seen above  there was timing fail  but implementation complete  is coming, basically  there is negative slack i.e;  set up -4.149 ns,hold 0.49 ns , WNS :-4.149 ns, TNS -2863.596 ns. How to remove negative slack/ timing fail? In Ethernet project as 3 clock we used in clocking wizard i.e clock_out1(166.667), clock_out2(200 MHZ ) and clock_out3(25 MHZ  ) why we use 166.667/200 MHZ frequency and 25 MHZ  clock_out3 is not connected to any port , why we required  clock_out3?

By hit and trail method reducing clock1 to 100 MHZ  

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Hi @neha,

In your xdc file I did not see this line:  set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk   in section 8.4 in the tutorial here has you make the xdc file eth_ref_clk and add that line to it. Have you installed the board files? The board files should constrain everything that you are constraining in the xdc file you took a screen shot of. In older versions of Vivado it looks like when you drag the Ethernet MII it does not create and axi ethernetlite IP block.I attached the IP block that it does create below. Make sure that you are using the axi ethernetlite IP. I have attached a screen shot of my block design as well. Looking at your block design I did not see that the axi ethernetlite was an issue.  I downloaded Vivado 2015.2 and went through the tutorial.I have added my project below. Try running my project and see if you are able to get it running.  

cheers,

Jon

Arty_echo_ethernetlite.zip

arty_ethernetlite_1.jpg

arty_ethernetlite_3.jpg

arty_ethernetlite_4.jpg

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Hi @neha,

So I had to delete the processor system reset_0 and  add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1. What board are you using? If you are using the Basys 3 are you also using the PmodNIC100 here? Also if you are using the board files for the basys 3 when you add and configure the Microblaze processor should automatically sets the reset to high.

cheers,

Jon

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Hi @neha,

I have not used the flash like this. I do not know if you can use the flash in this way. My understanding is that we used the 166.667 instead of 100 MHZ for clock 1 and 200 MHZ for clock 2 in the block design for the getting started with microblaze servers  and in the getting started with microblaze for the Arty-A7-35T to meet timing with the mig. The 25 MHZ clk is connected to the ethernet ref clock using the xdc to constrain the pin with the following:  set_property -dict { PACKAGE_PIN G18    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #         Sch=eth_ref_clk .

thank you,

Jon

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@jpeyron thanks going to  my  problem , making arty tutorial, installing 2051.2 vivado.

I am facing  problem in generating bit stream as shown in below attachment .I tried run your given  file but some archive problem is with that file .

after adding all Ethernet pins in xdc file  I am able to generate bitstream, as per your tutorial in step 11 some error is coming to generating bsp file. I try to mapped ethernetlite axi port as shown in msg.png, It already mapped now but its not validating  I tried 2-3 times .

Even port is mapped message box popped with not mapped, some how it not upadating

eer.png

detamsg.png

msg.png

sdk.png

xdc.png

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Hi abcdef,

I was able to get the microblaze "hello world" working for the Basys 3. Microblaze set to 128kb for local memory and no cache config.  I needed to add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1.  I am also making a Getting started with microblaze tutorial.

basys3_esc_2.jpg

basys3_esc_1.jpg

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