JColvin

Hi @mulzem,
The vouchers (provided to Digilent by Xilinx, so they ultimately have the end say on how the vouchers work) have been explained to me to work as follows:
For Digilent devices that use an FPGA not included with the free version of Vivado (such as the Genesys 2 with its Kintex-325 FPGA), you will receive a node-locked, device-locked voucher to be able to synthesize and generate bitstreams for designs on a single machine. You can redeem the voucher on the Xilinx Product Licensing site, https://www.xilinx.com/getlicense.html. Rather than locked to a particular version of the software (Vivado Design Suite vs Vivado ML vs HLx vs whatever branding is being used), the voucher is instead time limited for 1 year. During that one year, you will be able to update your Vivado/Vitis install to whatever newest version is available. After the one year period has completed, you will no longer be able to update to newer versions, but you will be able to freely continue to use the existing version that you do have. As for what IPs are available, I believe that all of the regular features (synthesis, ILA, base IPs like Zynq or Microblaze, Clock wizards, etc) are available in both the free Vivado ML Standard Edition and the paid (which the voucher would take of) Vivado ML Enterprise Edition, as per here: https://www.xilinx.com/products/design-tools/vivado/vivado-ml-buy.html. It is specifically the Kintex 325 FPGA that is locked behind the Enterprise/voucher. There may be some IPs that are not included with the voucher nor the free/paid version of Vivado. For the Genesys 2 specifically, this would be the Gigabit Ethernet PHY (TEMAC IP) and the DisplayPort IP licenses; https://digilent.com/reference/programmable-logic/genesys-2/reference-manual#software_support. If you wish to use these IPs beyond their own separate evaluation periods, you would need to pay Xilinx for them, same as Digilent would have to. From my understanding, all other "standard" IPs are freely included with Vivado. If you want to know the specific status of an IP, say Clocking Wizard, you can search for it on the Xilinx website and see if it is bundled with Vivado (as opposed to having an option to evaluate the IP).  I believe you should be able to transfer the license to a different machine. This is covered in the last question in Section 8 in the Xilinx/AMD FAQ on licensing, https://www.xilinx.com/products/design-tools/faq.html, "What happens when a license machine "dies" or is replaced". Again, Xilinx will have the end say on how the vouchers will specifically work (though I imagine the licensing site will also explain what you are getting before it uses the voucher), so any specific functionality questions I would recommend you ask Xilinx about. I do not have a license nor a Genesys 2, so unfortunately I do not have any specific experience to share.
Let me know if you have any questions.
Thanks,
JColvin

Hi @Salvador G,
The onboard FTDI chip on the Basys 3 allows for JTAG communication; that is how it can configure the FPGA: https://digilent.com/reference/programmable-logic/basys-3/reference-manual#usb-uart_bridge_serial_port.
I do not know the specifics of your setup, but the Adept SDK (part of the Adept download: https://digilent.com/reference/software/adept/start) has a JTAG subsection that might be of help to you.
Let me know if you have any questions.
Thanks,
JColvin

Hi @john-con,
I can confirm that the Arty A7 and Basys 3 both use speed grade 1 components.
I'm not certain off hand where you would readily determine this off of the chip labeling itself, but you can see the critical "-1" portion of the FPGA name in the right hand side of their respective Resource Centers, https://digilent.com/reference/programmable-logic/arty-a7/start and https://digilent.com/reference/programmable-logic/basys-3/start, of the "FPGA Part #" row.
As far as I know, zygot is correct that only Digilent's Genesys 2 has a speed grade 2 part.
Let me know if you have any questions.
Thanks,
JColvin

Hi @piwosz,
Digilent does not share the BOMs for our boards, but L1 (along with L2, L3, and L4) on the Zybo Z7 are a Panasonic EXC24CH900U.
Let me know if you have any questions.
Thanks,
JColvin

Hi @BMiller,
I received confirmation that the 2023.1 OOB material, both hardware and sw branches, is not yet ready; once it is completed (I do not know the timeframe on this) it will move out of the /next branch and into /master. You are also correct that the patch isn't needed in 2022.x onwards; Digilent will remove that note from the appropriate readme file.
However, regardless of the version of the tool suite used, the OOB demo uses the HDMI IP which needs its own license, as noted in the Reference Manual, https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual#software_support. I verified that the exact same error comes up on my license free machine for 2020.1 which the OOB material is based on:
Unfortunately, there is not a real workaround to this outside of removing the licensed IPs from the design and then regenerating the bitstream.
It might be possible (I have not tried nor investigated the following) to use some sort of DVI implementation instead, but you would not be able to get the 'full' HDMI 1.4b/2.0.
Thanks,
JColvin

Hi @bloggins666,
You are correct that the Baremetal tutorial (https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi) XSA would only set up material for what is present in the Block Design; in this case the ARM processor, the 4 buttons, and the 4 LEDs.
If you wanted to have access to all of the I/O pins on the PL side (and maybe anything extra on the PS side that isn't in the default configuration), you would need to create the associated design in Vivado, generate the bitstream for it, and then export the XSA which you would then import into Petalinux.
Adding access to the most of the other GPIOs will be fairly trivial. Simply add the Arduino styled headers and RGB LEDs to the block design as done for the LEDs in first part of the Adding GPIO Peripherals step (https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design). When right-clicking on each component in the Board tab to Connect Board Component, I would choose to create a new AXI GPIO IP (rather than an existing one). The second bit of that tutorial that shows how to manually assign pins is mostly there to show an alternate design flow within Vivado.
For connecting things like the HDMI ports, what I would personally do is to take the existing hardware design of the Arty Z7-20 HDMI input demo (https://digilent.com/reference/programmable-logic/arty-z7/demos/hdmi-input) and then add in the other GPIO pins like I described in the above paragraph.
Once the bitstream is generated and the .xsa is exported from Vivado, you'll be import it into Petalinux and create the BSP via petalinux-config if memory serves me. I've linked some additional resources on how this might be done in this post here:
Let me know if you have any questions.
Thanks,
JColvin

Hi @Ansh Waikar,
Personally, I probably would have used the 2022.1 release if you have the 2022.2 version of the Xilinx toolchain since it's going to be easier to debug while upgrading rather than debug if forced to downgrade, but I digress.
What you are describing sounds like the Xilinx linker script import bug; normally Digilent has a dedicated dropdown section on this included in our guides, but it is apparently missing from this Zedboard demo. I've added the relevant section into the guide you linked; it's expansion box called "Apply Fix for Linker Script Import Bug".
Hopefully this isn't the case for you, but then I had to fight with Vitis further since it said it couldn't find a .h file that was in the same directory as a different header file. I ended up resolving this by right clicking on the imported FMC_Pcam_Adapter_demo, selecting Properties, going to Paths and Symbols in the C/C++ General dropdown, and editing the offending non-existent directory to the correct file system folder. In my case, I had to change the C:/Temp/whatever_it_was to
D:\VivadoPrj\Zedboard-Projects\FMC-Pcam-Demo-23.1-R\Vitis\FMC_Pcam_Adapter_demo\src
(the beginning of the path should be changed to whatever is accurate for your computer, of course)
where the the first portion up until FMC_Pcam_Adapter_demo\src is where I had set up my Vitis workspace.

Let me know how it goes for you.
Thanks,
JColvin
 

Hi @dstebz,
There is a 3D model of the Pynq Z1 available in its Resource Center here: https://digilent.com/reference/programmable-logic/pynq-z1/start#design_resources.
Let me know if you have any questions.
Thanks,
JColvin

Hi @t0bi,
There should be no issue running the Pmod RS485 at 5 V; the datasheet for the embedded module (https://www.analog.com/media/en/technical-documentation/data-sheets/ADM2582E_2587E.pdf) even uses Vcc at 5 V (unless otherwise noted) in its Specifications table.
3.3 V is listed in the Reference Manual since all of the Digilent system boards with Pmod Host Ports operate with 3.3 V logic, but there isn't really any difference between operating at either of the two voltages from a pragmatic functionality standpoint.
If you wanted to be technical about it, the Typical Performance Characteristics graphs in the Analog Devices datasheet indicate that operating at 5 V consumes less current than when operating at 3.3 V (based on Figure 3 and Figure 4), but that's at the cost of operating at ~100 mW higher (at least for when I looked at 20 degrees C with an RL of 120 Ohms). Whether that is something you are concerned about in your system I do not know.
Thanks,
JColvin

Hi @llangaf,
I got confirmation from the design engineer that the JTAG HS3 (and other JTAG HSx modules) can be safely hot swapped.
Thanks,
JColvin

Hi @ayazar,
Your understanding is correct; the SPI programming refers to the ability to directly use / "send out" SPI signals to directly interface with SPI devices.
However, if the flash memory is set up in a master serial configuration with the onboard FPGA / SoC (like how Digilent's boards flash memories are set up where they are only accessible through the FPGA), you can still configure the flash memory through the Vivado Hardware Manager via the JTAG HS3 with the .bin file; it just gets routed through the FPGA.
Let me know if you have any questions.
Thanks,
JColvin

Hi @hlittle and @D@n,
The Pmod MicroSD card came in; the schematic is accurate with regards to the circuitry not being loaded. The pads and silkscreen are still present on the underside of the module (if you wanted to load the components yourself), but they are not populated in the production version.
I attached a couple of pictures of the module with my poor photography skills; I will put in a request for an official photo of the underside to be taken for the Resource Center and store page.
Thanks,
JColvin

Hi @Phil06,
You can certainly use jumper cables / wires to have the JTAG HS3 connect to a 6-pin JTAG interface instead, but it will be a bit finicky as asmi indicated.
Otherwise, it may be worth it to ask the Sales team if you can return/exchange the JTAG HS3 for a JTAG HS2 via the Sales and Order Support form available here: https://digilent.com/shop/shipping-returns/#return-policy (I have no access to any sales or shipping systems).
The main technical difference between the JTAG HS3 and the HS2 is that the HS2 does not have a PS_SRST pin to be able to reset the processor on Zynq devices during debugging operation, so as long as that is not an issue, there should be no problem to switch over to a JTAG HS2.
Thanks,
JColvin

Hi @KingKong,
Yes, if you want to design the display driver through HDL logic, then you can absolutely do that on the Arty S7 (I had mentioned the softcore processor since the design materials on the website were all Arduino based so I, incorrectly it seems, presumed you were intending to use the Arty S7 as a processor as well). Using FPGA logic will likely be more efficient as well since you won't have any overhead allocated to functionality that you don't plan to use in the softcore processor. It's more difficult to design of course, but then it will operate exactly as you choose.
Thanks,
JColvin

Hi @yildizabdullah,
I am not aware of any OpenOCD support for that particular cable.
Thanks,
JColvin

Hi @fbergmann,
I asked the design engineer most familiar with the SMT modules and they let me know that D14 is the most likely culprit for your problem. That particular part has too high of a capacitance value (30 pF according to the datasheet) for USB data lines. They also linked me an application note on this topic: https://assets.nexperia.com/documents/application-note/AN10753.pdf they had on hand since they've seen this issue in other designs wanting to use some extra diodes for ESD protection.
Thank you,
JColvin

Hi @RyanW,
You are correct that you will want to us the USB Host port that you'll want to power the board via a wall adapter as per the Reference Manual here: https://digilent.com/reference/programmable-logic/cora-z7/reference-manual#usb_host. On POR without any configuration the Type A USB OTG interface will not be providing any power because the CPEN output on the embedded Micochip USB3320 Transceiver Chip is at a logic low level so the power switch IC (IC4, on page 4 of the Cora Z7 schematic, https://s3-us-west-2.amazonaws.com/digilent/resources/programmable-logic/cora-z7/Cora+Z7_sch-public.pdf) will not enable the 5 V USBHOST_VBUS line.
Based on the USB3320 datasheet in section 5.6.3 (available for download from Microchip's website here: https://www.microchip.com/en-us/product/USB3320#document-table), CPEN is asserted by setting the DrvVbus or the DrvVubsExternal bit of the OTG Control Register (Table 7.1.1.7)
Thanks,
JColvin

Glad you resolved the issue!

Hi @Eminem,
Direct downloads for the images can be found for the Genesys ZU 3EG and the Genesys ZU 5EV on our Github here and here (SDImager recommended for Windows, "dd" for Linux) respectively (for the Rev D versions of the board), with the source for those images being available here and here.
There are some more instructions on using the out of box demo itself available on our reference site here: https://digilent.com/reference/programmable-logic/genesys-zu/getting-started#using_the_out-of-box_image.
Thanks,
JColvin

Partial supply chain, partial consolidation of product offerings, all business decision passed from the top down.
As far as I know the pinouts on both variants were the same; though the larger chip did have more FPGA resources with regards to things like BRAM and LUTs. I am not too familiar with the Petalinux side of things, but I will ask to see if Digilent can make the process smoother for the single core board.
Unfortunately, I have not heard any plans to bring the Zynq 7010 version of the Cora Z7 back into production and would not anticipate otherwise.
Thanks,
JColvin

Hi @Udayan Mallik,
I am not certain which exact error you are getting as I cannot see the error code in the Message console in your screenshots.
If I had to guess as what error your receiving, my guess would be that Vivado is saying that it cannot properly connect the pins 7, 8, 9, and 10 of the Pmod AD1. You can fix this by deleting the "pmod_jb" port and then right-clicking on the Pmod Out interface and choosing the Make External option.
After the interface has been made external and you make the wrapper for the project, you can find the correct names to explicitly name the Pmod pins in the .xdc by finding their names in the wrapper.v file. There are a couple of screenshots showing what I am attempting to describe in this post here:
Please let me know if you have any questions about this process.
Thanks,
JColvin

Hi @Udayan Mallik,
The Pmod ACL2 IP would not be able to acquire data from the Pmod AD1; while they both use the SPI protocol, the two modules have different SPI clock frequencies, registers to manipulate, and different bit lengths of data.
I would instead recommend you use the existing Pmod AD1 IP for the Pmod AD1.
Let me know if you have any questions.
Thanks
JColvin

Hi @crile,
Test and Measurement is the best location for WaveForms SDK questions; the engineer with best suite of knowledge to answer your questions (since they developed and maintain most if not all of the WaveForms SDK) is in Europe though so he likely won't respond until sometime tomorrow when he is back in the office (though I don't know if he has other R&D product development tasks that have been deemed higher priority, so it could be longer).
Thanks,
JColvin

Glad you were able to find the the material you were looking for!

Hi @brahmadev,
No license is required to generate bitstreams for the FPGA present on Digilent's Arty A7. You can verify this for yourself by seeing what device groups are listed as supported in the Vivado ML Standard Edition column in Xilinx's UG973: https://docs.xilinx.com/r/en-US/ug973-vivado-release-notes-install-license/Supported-Devices.
Thanks,
JColvin