Genesys zu 5EV - Errors on Getting Started with Vivado and Vitis for Baremetal Software Projects

[vcb1]

Hi,

I have recently bought the Genesys Zu 5EV and i have some problems with the tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

i have tried to reproduce all point step by step but i have some errors and i am wondering if there is some problem on the guide or with the versions. Here are all steps i have followed and the problems/errors i get:

Vivado part

In the step "Add a Zynq UltraScale+ Processor to a Block Design"

In the part that says "The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard." When they suggest to add a second clock, looks like it is not necessary, if I add it then I have an error afterwards about where to connect this pin.

To solve this issue I have removed this clock (i assume is not necessary to have a second clock here). Tehrefore i have also avoid the part of "add a Concat IP to your block design, and manually connect it to the pl_ps_irq0 port."

In step "Add GPIO Peripherals to a Block Design" part of  AXI_GPIO_BUTTONS

First i add the xdc file Genesys-ZU-5EV-D-Master.xdc for the contraints

In the guide it says "_the button interface to “btn_tri_io[#]”, where # is a decimal number, counting up from zero. When finished, save the file_.". However the button on the Genesys-ZU-5EV-D-Master.xdc starts on 2 until 6

I have re-named the file as suggested in the guide

However the guide says "In particular, the width of the GPIO interface must match the number of buttons available on the board." and i f i am not wrong in the genesys zu board there are 7 buttons not 5 (BTN0, BTN1, BTNL, BTNR, BTNU, BTND,BTNC) but the xdc file only defines 5, is this correct?
 

In step Edit the Address Map

 Here the values are different that the ones of the guide, but i have checked that there is no Assigning an segment to address 0 to avoid errors as explained in the guide. is this correct?

In step "Validate a Block Design"

it shows an error in the pin saxihpc0_fdp_aclk

Following the figures of the guide (even if they are not the same for the zynq ultrascate), I have connected the pin that produce the error (_saxishpc0_fdp_aclk_) to the pin _pl_clk0_ (clock) pin. Sfter that the validation is ok, is this correct?

The validation now is ok, but it shows the following warning messages

 

 

Vitis part

In the "Create a New Application Project"

When i have to select the Aplication project details. Which Processor should i use? In the guide the picture is different. Is it correct to use the first one _psu_cortexa53_0_ ?

As suggested in the guide " Change the BTN_MASK and LED_MASK macros so that they contain a number of '1's equal to the number of buttons and leds connected to the GPIO peripherals in the hardware design." Here i assume is 5 for buttons and 4 for leds as i did it in the vivado part is this correct? how do i know the buttons and leds connected to the GPIO peripherals in the hardware design ?

 

In the step "Launch a Vitis Baremetal Software Application"

When i try to make  _Run as → 1 Launch on Hardware (Single Application Debug)._ It pops up an error window.

 

 

If i run with the option " Launch on emulator" looks like is working, but i do not knw how to test the buttons and leds there.

Many thanks,

 

log_build_vivado_project.txt

Edited April 12, 2022 by vcb1

[thinkthinkthink]

You should follow this Genesys-ZU Hello World Demo Project Guide to get a better idea on how to work with our Genesys-ZU variants before trying anything else.

[vcb1]

7 minutes ago, thinkthinkthink said:

You should follow this Genesys-ZU Hello World Demo Project Guide to get a better idea on how to work with our Genesys-ZU variants before trying anything else.

Yes, i did already the Hello world demo and it works fine. 

Now i am trying to follow the https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi.

 

 

Edited April 11, 2022 by vcb1

[thinkthinkthink]

Also you need a post-implementation bitstream for the project to work on the board. So show us the Message tab and the Implementation log to see why vivado couldn't implement your design. The Synthesis log you uploaded wasn't enough.

[vcb1]

17 hours ago, thinkthinkthink said:

Also you need a post-implementation bitstream for the project to work on the board. So show us the Message tab and the Implementation log to see why vivado couldn't implement your design. The Synthesis log you uploaded wasn't enough.

Sorry there was a mistake from my side.  i've realized i had an error renaming the buttons of the Genesys-ZU-5EV-D-Master.xdc file. Now i can generate the bitstream as explained in the guide. Tehrefore the part of the vivado is ok.

However i repeat the process in the vitis part and i get the same error.  I am not sure if the part of the "Change the BTN_MASK and LED_MASK macros" i did it correct. should i add the number in binary format? i mean i have tried:

but i sitll have an error

 

and here the log of the xsct console

xsct_console_log.txt

I include also the xparameter.h file where the GPIO are defined xparamters.txt

 

Many thanks for your help!

 

 

Edited April 12, 2022 by vcb1

[John J]

@vcb1

I don't think that "Getting started" applies to UltraScale+ boards.  UltraScale+ devices require a first stage boot loader, FSBL.  Specifically, the Genesys-ZU also requires a custom boot loader from Digilent to support the DDR.  See the first paragraph in section 3 of the reference guide.

I had the same issue, as this is a requirement that is not very prominently documented.  You can see the discussion here.

The gist of it is that I ended up starting with the "Hello World" app specifically with 2020.1 of Vitis to get anything working.  2021.2 can be made to work but has issues with things like programing the onboard QSPI flash.

Edited May 2, 2022 by John J

[lhgsam]

On 5/2/2022 at 9:45 PM, John J said:

@vcb1

I don't think that "Getting started" applies to UltraScale+ boards.  UltraScale+ devices require a first stage boot loader, FSBL.  Specifically, the Genesys-ZU also requires a custom boot loader from Digilent to support the DDR.  See the first paragraph in section 3 of the reference guide.

I had the same issue, as this is a requirement that is not very prominently documented.  You can see the discussion here.

The gist of it is that I ended up starting with the "Hello World" app specifically with 2020.1 of Vitis to get anything working.  2021.2 can be made to work but has issues with things like programing the onboard QSPI flash.

I can confirm this answer works for me.

[Richm]

I could be wrong, but don't you want to use a full power domain ( not LP ) axi master to connect the A53s to the FPGA?

Also, did you start with Vitis by creating and building a platform using the xsa file generated by exporting the hardware in Vivado?