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  1. thinkthinkthink's post in Hello word bitstream generation error for CoraZ7 was marked as the answer   
    I know it might be a little misleading but your GPIO input port is not called "btn" but "btn_tri_i" so your constraints should be: btn_tri_i[0] and btn_tri_i[1].
    Open the wrapper file by double clicking on it and you'll see that your design has no ports named "btn". When manually constraining ports you should always check the ports declared under Entity inside the wrapper file to get the complete port name.
  2. thinkthinkthink's post in microblaze project using adt7420 on nexys4 ddr was marked as the answer   
    If you're using the TMP2 Pmod then you only need the MicroBlaze processor, the MIG7 IP and an IIC IP to write to and read from the adt7420. It says in it's datasheet that it has a 16-bit ADC so there's no need to use the XADC.
    Also make sure to give the TMP2'S Reference Manual a read through.
  3. thinkthinkthink's post in Trouble with LVDS output on a Cora Z7-10 was marked as the answer   
    The JA pins are on Bank 34 which is supplied from VCC3V3 (page 8 of the Cora Z7 schematic) so no way you could do 2.5 V.
  4. thinkthinkthink's post in Connecting the uartlite signals from the PL through Pmod pins on a ZedBoard was marked as the answer   
    set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_rxd}]; # "JA3"
    set_property -dict { PACKAGE_PIN AA9 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_txd}]; # "JA4"
    Here, fixed your constraints for you, it's that easy.
  5. thinkthinkthink's post in Nexys A7-100T PMOD Pin Functionalities Missing? was marked as the answer   
    That's because those PMOD ports are connected to FPGA pins which can be reconfigured (inside the FPGA) for a lot of different functions/protocols while on the microcontroller those are wired to peripheral pins that only have a limited set of hard-wired functions. On an FPGA board you can make a custom design and be able to literally connect 4 different I2C devices to 1 PMOD port and have 4 different SCL and 4 different SDA lines (you'll need a bunch of wires but whatever). Basically you can customize those PMOD pins however you like/want/need.
  6. thinkthinkthink's post in Why is the Pmod HYGRO only able to read from the top pins of the ZYBO Z720? was marked as the answer   
    HUGE DISCLAIMER! You'll have to write your own I2C driver using the iic functions in Xilinx's embeddedsw repo (XIic_MasterRecv, XIic_MasterSend etc.).

    Add the two AXI IIC IPs to your block design and let Run Connection Automation do its job or you can manually make the IIC ports external. Then go to our XDC Repo and get the Zybo-Z7-Master constraints file. 
    Right click on Constraints and select Add Sources. 

    Click on Add Files and look for the .xdc file wherever you downloaded/saved it on your PC. Make sure Copy Constraints files into project is checked, this makes it so if you modify this .xdc file (which you will) you'll still have a fresh unmodified original which can then be imported into other projects.

    Uncomment the lines corresponding to the Pmod port which you'll want to use, in this example I'm using JD but because of the HYGRO and AQS pmod pinout you'll only need to uncomment jd[2], jd[3] and jd[6], jd[7].

    This is the pinout for the PmodAQS and you might want/need to also use the IO/INT or WAKE/RST pins so make sure to read through its Reference Manual.

    Make the following changes in the XDC, Validate Design, Generate Bitstream and you're good to go.


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