One thing to be careful with is the S2MM (input to ps) must be set up first, before the MM2S channel. If you try streaming data into the DMA before the channel is set up it will lock up. I found this mistake in Xilinx's own example code. I would look closely at the DMA driver code, it could easily have bugs in it. From my experience with both STM and Xilinx, I would say that driver code is often written by inexperienced programmers and not necessarily properly tested. Read the AXI DMA data sheet as well. Using the DMA is basic mode is really simple and requires just 2 register writes per channel. Use this sequence:
1) Set the run bit ( only need to do this once )
2) Wait for DMA idle ( only after the first transfer )
3) write the S2MM address and transfer length (bytes)
4) write the MM2S address and transfer length
I use an AXI DMA to transfer 64 32-bit words to 8 different IPs by separately multiplexing tvalid. Tready is tied high as I designed the IP to always be ready. The DMA has internal fifos and has no trouble transferring all 64 words in a single burst of 64 clock cycles. I use the OCM, which as been set to non-cachable, as buffers for the DMA transfer.
