Richm
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Dunno exactly but it is very helpful to use a FIFO between the data generator and the UART transmitter. That way you can just write the output data ( one byte per clock cycle using AXI stream) to the FIFO and the communication between the FIFO and the UART takes care of loading bytes when the UART is ready.
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I've found Xilinx driver code to be obtuse and buggy while writing my own for the UARTS, timers, and other simpler modules using the TRM is pretty easy. More than once I've had the experience of studying/debugging the provided code only to realize that I could have it working already if I'd started with the TRM and set set/clear the bits myself. I really like MPSOCs because the combination of FPGA and PS makes it easy to create your own peripherals in the fabric specific to the part and use. For instance, if I was interfacing to an SPI display I would write Verilog IP that could do the SPI and higher level maintenance of display with an AXIlite interface so the processor can simply write chars to the local buffer and not be concerned with the rest of the process.
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Dunno, I've experimented with many PL only designs but I always use the PL clock & a clock wizard. If you click on the 'board' tab with the block design open, you should see a clock source listed that you can click on and add to your design. It will create the necessary ports, constraints and a clock wizard that you can modify. Note that by PL only I mean no PS in the block design and using the Vivado hardware manager only.
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No, the timing isn't super critical. Your RX module should restart with the leading edge of the start bit so that any accumulated error only potentially affects the bits within the byte, not byte to byte. If you use a high enough frequency input clock you can simply count clock cycles to time everything, the error will not accumulate. Also, you want to use a metahardening block in the same clock domain on the rx pin input. On the TX side you will probably want a large enough fifo so as to avoid having to handle the back pressure up stream.
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artvvb reacted to an answer to a question:
Zybo Z7-20 JTAG run not working but debug works
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Did you simulate? Sounds like something like a counter is not properly initialized and it takes about 10 minutes for it to roll over.
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It could be a problem with the AXI bus in the PL. Double check the assigned addresses in Vivado and the xparameters.h file that Vitis created when you built the platform. An address mismatch will hang the AXI bus and appears to crash the entire system.
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artvvb reacted to an answer to a question:
Eclypse Z7, Using 2 Channels of DAC simultaneously
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Udayan Mallik reacted to an answer to a question:
Eclypse Z7, Using 2 Channels of DAC simultaneously
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Eclypse Z7, Using 2 Channels of DAC simultaneously
Richm replied to Udayan Mallik's question in Embedded Linux
C ( and C++?) are highly typed languages so it is worth learning to be precise with constants and data types to avoid unexpected errors. In C, 2 != 2.0f != 2.0. The first is an integer, the second a single precision float and the last is double which is what C defaults without the 'f' suffix. Yes, the compiler can automatically convert in some cases but it is better to be completely explicit. For example, your code maybe working just fine but you are implicitly using double (64 bit) floating point. -
I also had a quick look at your code. It looks like you are setting a flag in the isr for the main loop when a character is available? This would be the same as polling ( blocking ) in the main loop with an extra layer added on top. What you want to do read characters in the isr into a double (ping-pong) buffer until the rx fifo is empty and then set a flag and switch buffers when the command framing character ( usually cr or lf ) is received. What I usually do is set the flag to 1 or 2 to tell the main loop which bank of the rx buffer to read. Also, be aware that sending a string longer that 16 chars will cause blocking on the tx side. I skip the character echo and transmit a simple ack/nack ( "OK"/"Error" ) depending on the results of the command parser.
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SPI is a particularly simple protocol. Designing an HDL SPI master is an excellent beginners exercise - study the a/d data sheet, it should have everything you need to get started. Can I help any more than that? No. VHDL gives me a headache. I like the clarity & simplicity of Verilog.
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artvvb reacted to an answer to a question:
Pmod issue
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One also needs knowledge and experience with DSP since that's what you're doing. It took me a couple of years of Sundays to finally get comfortable with Verilog, AXI and Vivado including taking a bunch of Xilinx on-demand classes. Learning how to use the simulator and knowing how to interpret the results is perhaps the most critical part.
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This is a bit embarrassing, but I discovered after buying another I2S PMOD that I wasn't driving the MCLK ( PMOD in slave mode ) at the correct frequency ratio to the LRCLK. A simple change to assign the MCLK to a different bit in the clock counter fixed the problem. This error didn't affect the D/A just the A/D thus explaining what I was observing. In my defense I think the data sheets are a bit confusing, but rererereading them fixed the problem.
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This is maybe a good application for hardware acceleration?
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I could be wrong, but don't you want to use a full power domain ( not LP ) axi master to connect the A53s to the FPGA? Also, did you start with Vitis by creating and building a platform using the xsa file generated by exporting the hardware in Vivado?
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Can you elaborate as to what kind of underlying issues might occur when using direct register access for a GPIO? I've never used the PS GPIO, but the AXI GPIO couldn't be simpler - 1 data and 1 data direction register per channel. In my experience, the Xilinx driver code is way over complicated to the point of being hard to use and debug. More than once I have started with Xilinx example code and then ended up doing what I should have done all along - read the documentation and read/write the registers myself, just like I have done many times in the past with HC11/16s, PICs, AVRs and ARM microcontrollers.
