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John J

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Topics posted by John J

  1.  

    Question: Programming the flash from Vitis on a Genesys-ZU

    By John J, in FPGA

    • Awaiting best answer
    • 1 vote
    • 13 answers
  2.  

    Question: With two Genesys-ZU 3EG boards, one boots from QSPI the other fails in the FSBL

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  3.  

    Question: Genesys ZU Bare metal multi-core linker script configuration

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  4.  

    Question: Genesys ZU: Digilent FSBL causes strange behavior when run twice

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 1 answer
  5.  

    Question: Zynq Ultrascale+ example with FreeRTOS using interrupts on a UART or other interrupt source

    By John J, in FPGA

    • Awaiting best answer
    • 1 vote
    • 2 answers
  6.  

    Question: SD data I/O configuration for Genesys ZU boards

    By John J, in FPGA

    • Has best answer
    • 0 votes
    • 2 answers
  7.  

    Question: Using the Genesys-ZU UART1 with the bare metal driver

    By John J, in FPGA

    • Has best answer
      
    • 0 votes
    • 20 answers
  8.  

    Question: Accessing a development board in Linux with multiple users

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 1 answer
  9.  

    Question: I can create a working bare metal project for a Genesys-ZU in Vitis 2022.1, but it has one issue...

    By John J, in FPGA

    • Awaiting best answer
      
    • 0 votes
    • 6 answers
  10.  

    Question: Git workflow issues

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 4 answers
  11.  

    Question: Genesys ZU debugging error

    By John J, in FPGA

    • Awaiting best answer
    • 0 votes
    • 16 answers
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