Genesys ZU debugging error

[John J]

I am getting the following error when debugging a newly created Vivido/Vitis bare metal "hello world" project using the steps below.  I am just following tutorials by Digilent and Xilinx.  I've seen other posts with the error, but I have not yet found a solution.

I get the following error.

10:00:24 INFO   : 'bpremove $bp_0_22_fsbl_bp' command is executed.
10:00:24 INFO   : Context for processor 'psu_cortexa53_0' is selected.
10:00:24 INFO   : Processor reset is completed for 'psu_cortexa53_0'.
10:00:24 ERROR  : Memory write error at 0x0. Cortex-A53 #0: EDITR not ready

The Digilent supplied "hello world" project works, but I have to create a soft link the FSBL in the correct place to make it go.

If I replace the FSBL in my project with the one from the Digilent supplied "hello world" projecct, debugging the application works.

 

Here is what I did to create the Vivado and Vitis projects:

• Development Environment: Vivado/vitis 2021.2 running on Ubuntu 20.04
• Board: Genesys-ZU-5EV Rev. D
• Board files: genesys-zu-5ev/C.0/*  (https://github.com/Digilent/vivado-boards/tree/master/new/board_files, Aug 10, 2021)
• Constraints file: Genesys-ZU-5EV-D-Master.xdc (https://github.com/Digilent/digilent-xdc, Jul 20, 2021)

 

Vivado

1. Create a top-level project directory
2. Start Vivado
3. Create a project in a subdirectory under the top-level directory
4. Select the project type as an RTL project
5. Skip the “Add Sources” step
6. Under “Add Constraints” step, add the Genysis-ZU-EV5 constraints file and enable the “Copy constraints file into project” option
7. Select the boards tab and select the Genysis-ZU-5EV board
8. Create a block design and name it like ProjectName_bd
9. Add a Zynq_Ultrascale+_MPSoC to the block design
10. Run block automation with the default settings
11. Connect pl_clk0 to both maxihpm0_lpd_aclk and saxihpc0_fpd_aclk
12. Under the Sources tab of the block diagram, open the constraints file in the editor and uncomment the firs two lines that start with “set_property”
13. Under the Sources tab, select the block design file and create an HDL wrapper
14. Click on Generate Bitstream and click through the dialogs
15. Under the File menu export hardware
16. Include bitstream
17. Export the hardware as an XSA with bitstream

 

Vitis

1. Start Vitis
2. Create an application
3. Create platform form XSA file
4. Select the hello world template
5. Build it
6. Debug single application

 

Edited February 4, 2022 by John J
Formatting

[JColvin]

Hi @John J,

I am in the process of downloading 2021.2 (garsh these downloads get bigger every year) and will let you know what I experience. From your very detailed description, you seem to have done every step correctly so I don't have anything to directly recommend to try differently at the moment.

Thanks,
JColvin

[John J]

Hi @JColvin,

I would appreciate any help you can provide.  I also tried separate steps of creating a platform project and application project, as per the following steps from Xilinx.  This produced the same result.  This method produces a project structure more like the Digilent Hello World project, but produces the same error.

https://xilinx.github.io/Embedded-Design-Tutorials/docs/2021.1/build/html/docs/Introduction/ZynqMPSoC-EDT/ZynqMPSoC-EDT.html

Thank you for your help.

John J

Edited February 8, 2022 by John J
Formatting

[Richm]

Vitis is very confusing at first. I believe you should create the platform first and then add the application.

What processor are you targeting? Make sure to check the 'generate boot components' box when creating the platform. Double click on the 'platform.spr' file in the explorer and you should see domains for both the fsbl and the pmufw. Are you building the platform before adding the application?

[John J]

Hi @Richm,

I apologize for not getting back to you sooner.  I'm currently on travel.

I did follow the Xilinx tutorial noted above for creating a platform project and adding the application.  This crated projects with a different structure, but gave me the same error.  I have not checked if it occurred the exact way as the other projects.

I'm targeting the Ultrascle+ 5EV on the Genesys Zu board.  I did check the generate boot components.  Yes, I do build the platform first or do a build all.   I get the same result either way.

I believe that both domains are created, but I will have to verify that when I have access again.

Thank you for your help.  any suggestions would be appreciated.

[BogdanVanca]

Hello @Richm,

 

We found out that there is a "bug" with the "PSU__DDRC__DDR4_ADDR_MAPPING" parameter from the board preset file, that went under our radar. This parameter needs to be disabled in order to  return to the static DDR configuration operation in psu_init.c and the FSBL.  For that,  you need to go to \Xilinx\Vivado\2021.1\data\xhub\boards\XilinxBoardStore\boards\Xilinx\genesys-zu-5ev\C.0 and replace the existent preset file with the one that is attached to this message.

After that, open your Vivado project and run in your tcl console the fallowing command:

report_property [get_ips design_1_zynq_ultra_ps_e_0_0] -regexp .*PSU__DDRC__DDR4_ADDR_MAPPING.*

If the preset was correctly applied, you should see the fallowing message:

INFO: [Vivado 12-5777] IP Instance 'design_1_zynq_ultra_ps_e_0_0' cannot be used in a module reference:
Property                             Type    Read-only  Value
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING  string  false      0

If not, open your Zynq Ultrascale+ MPSOC IP and go to Presets->Apply Configuration, and browse to the preset that I gave you.

Run again the command, and verify if "CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" is 0.

Note: In your project "design_1_zynq_ultra_ps_e_0_0" is the name of the Zynq MPSoc IP. You can find the name of your Zynq MPSOC by running the fallowing command:

get_ips

and searching for the one that has the "zynq_ultra_ps_e_0_0" extension.

If this doesn't solve your issue, please let me know.

This change will be available in a future minor revision, but I thought  that there is no need to make you wait until we publish it.

 

Best Regards,

Bogdan Vanca

preset.xml

[John J]

Hi @BogdanVanca,

I replaced the board file and created a new project by creating the platform and adding the application, and got the same error.  Essentially, I followed the Xilinx tutorial referenced above.

The parameter shows up correctly as 0.

Do you have any other suggestions?

I appreciate your help.

[BogdanVanca]

Hi @John J,

Your problem may be caused by not using our custom fsbl file. Our "Hello World" project adds the following https://github.com/Digilent/embeddedsw/tree/6e9e2fa973f2c27d3f979f3c07afdbe616f694a4 repository into the ws. One solution would be to manually clone the embededsw repository, and add it into your Vitis workspace.

Xilinx ->Software Repositories-> New-> browse to the repository 

 

Note: You need to delete your existing FSBL before you start re-building a new one.

Best Regards,

Bogdan

[John J]

Hi @BogdanVanca,

You are correct that I did not use the custom code.  The custom code is only referenced once in the Digilent documentation for the ZU board, and the reference is in a bit of an odd location.  It is very easy to miss.

It would be more than very helpful to have a description of how to create a working application project from scratch.  Unless I'm missing something, there is no simple way to actually import the custom repo into an existing Vitis project.  There are several steps that would have to be taken to actually turn the repo into a Vitis project that could be built and edited within Vitis as part of an application project.

I built the custom FSBL separately, but there is also no Digilent specific documentation that I can find to help with that either.  The repo contains lots of directories with make files and a readme from Xilinx that has instructions on how to build, but that procedure does not produce a working FSBL for the Digilent board.

How do you build a working FSBL for the Genesys ZU 5EV board with that code?

I've tried both the commit that you sent, and the latest without producing a working FSBL.

Thank you for your help in advance.

John J

[elodg]

Our repo is a fork of the embeddedsw Xilinx repo. This sw lib comes with the Vitis installation and workspaces use it by default to generate an fsbl project for example.

All you need to do is to add our repo checked out at the right branch as a local software repo in the Vitis workspace. Regenerating fsbl will then pull source code from there.

We will extend the Getting Started guide with a start from scratch section.

As a general recommendation start from your example projects. For the GZU these pull in the right repos and generate projects correctly. 

[John J]

Thank you @elodg,

I have been using the Hello World project as a starting point--somewhat successfully.

There are a couple of issues that I have run into.

First, I'm getting inconsistent results while updating the hardware platform in the Vitis project.  After an update, there are sometimes references to files that don't exist, but the next time I work through the exact same procedure, there is no problem.  I do believe this is an issue with the Hello World project being used in Vitis 2021.2.  The upgrade and directory reorganization appears to be flakey.

Also, as a side comment, I see occasional references to files in the project configuration with Windows file names that still exist after longer periods of development in a Linux environment.  I know... It's more than likely a Vitis issue.

Another thing I noticed is that it appears that not all of the board features are defined for the GZU boards as they are in other Digilent products.  An example would be the LEDs and switches.  I may be missing something here.

I would definitely appreciate the added information to the Getting Started page, as this would avoid having to deal with the project version issues caused by the newer Vitis software, and allow starting with a pristine hardware project.  I'm still not clear on how you add the repo from the description you gave.  When I tried to do that as described by BogdanVanca, there were many file reference issues.  This also may be a Vitis version issue.

Thanks again.

John J

[elodg]

Versioning with Xilinx tools is problematic. You should be using the same version the project was generated in.

We have seen issues with absolute paths stored in project settings, Xilinx quirks all over.

User I/O interfaces like LEDs and switches should be working in board flow, we will verify.

Add repos here:

[John J]

@BogdanVanca,

Is there an updated preset.xml file for the genesys-zu-3eg/D.0?

I don't see any recent updates to the repo, and I'm getting a 3eg board soon.

John

[BogdanVanca]

Hi @John J,

Our latest preset is https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-3eg/D.0 

For now, we don't have any plans to bring in any updates. If you are facing any issues, please let me know.

Best Regards,

Bogdan Vanca

[singhhgurii8]

I've tried both the commit that you sent, and the latest without producing a working FSBL.

[elodg]

How do you know it is not working? What is printed on the console? What is the status of the LEDs?

[John J]

Hi @singhhgurii8,

I had too many issues creating a project from scratch and mainly could not get the the custom FSBL repo to import into a project correctly.

I ended up starting with the Digilent Hello World app, creating a customized Vivado design, and updating the platform in the Vitis project.

It is not ideal, but at least I have a starting point.

I did also modify the constraints file so that the signal names in it match up with the signal names in the board files.  I'm not an experienced FPGA developer, so I just did it because it made sense to me.  It started working after that, but I have not verified if was required.

John J