Genesys ZU Bare metal multi-core linker script configuration

[John J]

We are currently developing a 6 core bare metal project on a Genesys ZU board.  We get some odd results after modifying the linker script DDR configuration to accommodate all cores.  (I'm ignoring OCM,  ATCM and BTCM for this question.)

Is there any reason the idea of assigning a 1/2 GB of DDR to each core as below would cause issues?

   psu_ddr_0_MEM_0 : ORIGIN = 0x000000000, LENGTH = 0x020000000
   psu_ddr_0_MEM_1 : ORIGIN = 0x020000000, LENGTH = 0x020000000
   psu_ddr_0_MEM_2 : ORIGIN = 0x040000000, LENGTH = 0x020000000
   psu_ddr_0_MEM_3 : ORIGIN = 0x060000000, LENGTH = 0x01FF00000
   psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x020000000
   psu_ddr_1_MEM_1 : ORIGIN = 0x820000000, LENGTH = 0x020000000
   psu_ddr_1_MEM_2 : ORIGIN = 0x840000000, LENGTH = 0x020000000
   psu_ddr_1_MEM_3 : ORIGIN = 0x860000000, LENGTH = 0x020000000

 

R5#0  app, psu_ddr_0_MEM_0
R5#1  app, psu_ddr_0_MEM_1
A53#0 app, psu_ddr_1_MEM_0
A53#1 app, psu_ddr_1_MEM_1
A53#2 app, psu_ddr_1_MEM_2
A53#3 app, psu_ddr_1_MEM_3

Thank you for your help.

[Ionut]

Hi John J,

I apologize for answering so late to your post.

Have you used our Hello World Demo as a starting point for your project (https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world)? The FSBL inside it has been custom modified for Genesys ZU, and it might solve the problem for you.

Also, what is the purpose of assigning a 1/2 GB of DDR to each core? Is it for reading/writing user data? If so, you should make sure you do not overwrite any memory area where your application code is present. lscript.ld in Vitis can help you identify and avoid the respective area.

 

Best Regards,

Ioan.

[John J]

Hi @Ionut

I have started with both the Genesys FSBL 2020.1 and 2022.1 from the following location.

https://github.com/Digilent/embeddedsw/tree/genesys-zu-22.1/lib/sw_apps/zynqmp_fsbl/src

The purpose of assigning 1/2 GB to each core is to give the cores unique RAM for the core's own code and data.  I'm just letting the linker automatically allocate the space for each section, as is the case for the two memory blocks in the Digilent Hello World app, here.  Since I am letting the linker allocate the memory within the 1/2 GB memory block, I shouldn't have any possibility of overwriting anything within the block.  Right?

I was just looking for verification that my approach was valid.

Thank you for your help.

JJJ