Zynq Ultrascale+ example with FreeRTOS using interrupts on a UART or other interrupt source

[John J]

(This question has been posted at Xilinx, but I'm posing it in this forum in case someone has run into the same issue here.)

The FreeRTOS example that Xilinx provides does not run on our Zynq UltraScale+. We have enabled the appropriate timers in Vivado, but the interrupt handler is never called in our applications running on a FreeRTOS domain. Are there any other configuration options that are required to make this work?

Does anyone have an example of using interrupts with FreeRTOS on an UltraScale+.

We would like to see a working example using a UART, but any device that we can easily generate an interrupt from would helpful.

Thank you for your help!

We were using the following example.

https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c

[John J]

Has anyone gotten any basic interrupt code to work using FreeRTOS on the Genesys ZU board?

[Alex D]

Sadly, Xilinx drivers and examples almost never work. 

 

In this case, I think you are missing the GIC setup code. You must setup the GIC before any interrupts can be handled. 

Here is the GIC setup function from  my application. 

 

Once setup, you must install the correct interrupt handlers. This is not done for you, and must be done as part of the UART setup sequence. 

    xStatus = XScuGic_Connect( &xInterruptController, XPAR_XUARTPS_1_INTR,  (Xil_ExceptionHandler) prvUART_Handler, (void *) &xUARTInstance );
    configASSERT( xStatus == XST_SUCCESS );

 

XScuGic xInterruptController;

static s32 initGIC()
{
    XScuGic_Config *pxGICConfig;

    /* Ensure no interrupts execute while the scheduler is in an inconsistent
    state.  Interrupts are automatically enabled when the scheduler is
    started. */
    portDISABLE_INTERRUPTS();

    /* Obtain the configuration of the GIC. */
    pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );

    /* Sanity check the FreeRTOSConfig.h settings are correct for the hardware. */
    configASSERT( pxGICConfig );
    configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) );
    configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS );

    /* Install a default handler for each GIC interrupt. */
    return XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );

}