Genesys ZU: Digilent FSBL causes strange behavior when run twice

[John J]

We have a multi-core bare metal project that works consistently after power has been applied to the Genesys ZU 3EG board.  This applies to both running/debugging in Vitis 2022.1 and using an XSCT run script.

If we run the multi-core project again, without cycling the power on the Genesys ZU board, the application fails to receive consistent serial data on it's AXI UART Lite ports using interrupts.

After the FSBL has been run once, if we disable the use of the FSBL for any follow on runs, the application receives the correct data.

On the other hand, if we just run single cores, the individual applications work fine with the FSBL always enabled.

Why would a multi-core project fail due to running with the FSBL after a previous run, even with a system reset between runs?

Edited May 12, 2023 by John J
Bad title

[Ionut]

Hi John J,

 

First of all, I apologize for answering so late to your post. I realize it must be frustrating to encounter an issue and to not receive help for so long.

Regarding your problem, what FSBL have you used? Have you tried our Hello World Demo as the starting point for your project (https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world)? This demo contains a FSBL customized for the Genesys ZU; for example, it contains a workaround for a known Vivado issue.

If the FSBL from our Hello World demo does not fix your issue, could you try to debug your software project in Vitis step-by-step and let me know what the debugger tells you?

Best Regards,

Ioan.