Getting 2 warnings when I generate a Bitstream for my Zybo Z7, I can't understand why.

[Stryker180]

this are the warnings: [DRC NSTD-1] Unspecified I/O Standard: 7 out of 19 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: J1_mod[6], J1_mod[5], J1_mod[4], J2_mod[6], J2_mod[5], J2_mod[4], and Good_G.[DRC NSTD-1] Unspecified I/O Standard: 7 out of 19 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: J1_mod[6], J1_mod[5], J1_mod[4], J2_mod[6], J2_mod[5], J2_mod[4], and Good_G.

[DRC UCIO-1] Unconstrained Logical Port: 7 out of 19 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: J1_mod[6], J1_mod[5], J1_mod[4], J2_mod[6], J2_mod[5], J2_mod[4], and Good_G.
 

this is the code in VHDL: 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity F15_Altitude_Warning_System is
    Port (
        CLK         : in std_logic;
        Control_UP  : in std_logic;
        Control_Down: in std_logic;
        J1_mod      : out std_logic_vector(6 downto 0);
        J2_mod      : out std_logic_vector(6 downto 0);
        Warning_R   : out std_logic;
        Good_G      : out std_logic
    );
end F15_Altitude_Warning_System;

architecture Behavioral of F15_Altitude_Warning_System is
    signal Seven_segment_J1 : std_logic_vector(6 downto 0) := "0111111";
    signal Seven_segment_J2 : std_logic_vector(6 downto 0) := "0111111";
    signal counter : integer := 0;

begin
    process(CLK, Control_UP, Control_Down)
    begin
        if rising_edge(CLK) then
            if Control_UP = '1' then
                if counter < 7 then
                    counter <= counter + 1;
                end if;
            end if;
        end if;
    end process;

    process(counter, Control_Down)
    begin
        case counter is
            when 1 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "0000110";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 2 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "1011011";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 3 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "1001111";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 4 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "1100110";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 5 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "1101101";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 6 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "1111101";
                Good_G <= '1';
                if Control_Down = '1' then
                    Seven_segment_J1 <= (others => '0');
                end if;
            when 7 =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "0000111";
                Good_G <= '1';
                Warning_R <= '1';
            when others =>
                Seven_segment_J1 <= "0111111";
                Seven_segment_J2 <= "0111111";
                Good_G <= '0';
                Warning_R <= '0';
        end case;
    end process;

    J1_mod <= Seven_segment_J1;
    J2_mod <= Seven_segment_J2;
    

end Behavioral;
 

this are the constraints: 

set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS18 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { CLK }];

##Buttons
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS18 } [get_ports { Control_UP }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS18 } [get_ports { Control_Down}]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

##LEDs
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS18 } [get_ports { Good_G[0] }]; #IO_L23P_T3_35 Sch=led[0]
#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

##RGB LED 6
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS18 } [get_ports { Warning_R }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

## Pmod Header JC
set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS18     } [get_ports { J1_mod[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS18     } [get_ports { J1_mod[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS18     } [get_ports { J1_mod[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS18     } [get_ports { J1_mod[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { J1_mod[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { J1_mod[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { J1_mod[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#
## Pmod Header JD
set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS18     } [get_ports { J2_mod[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS18     } [get_ports { J2_mod[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS18     } [get_ports { J2_mod[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS18     } [get_ports { J2_mod[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { J2_mod[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { J2_mod[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { J2_mod[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { J2_mod[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]

Note: I tried to use LCVMOS33 but still it doesn't work.

[artvvb]

Hi @Striker

Please make sure the port names in your constraints precisely match the names in the top module and that all top module ports are constrained. 1. Several necessary constraints are commented out, like J2_mod[6], see the leading "#" character on its line. 2. Bus syntax should not be mixed with single-bit port syntax, as in Good_G, which should not include the [0] in the constraints.

Thanks,

Arthur