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Found 9 results

  1. Hello, I am having some difficulties getting LVDS to output on my Cora Z7-10. I've tried boiling it down to its most basic form of just trying to output a 10Mhz clock through on one of the differentially routed PMOD ports (JA), but I'm still not seeing any output on my oscilloscope. Can anyone help in in understanding what's going wrong here? Has anyone else gotten LVDS to work correctly on this board's PMOD ports? I tried looking at some other designs like the HDMI TMDS33 through PMOD that was posted on this forum before and I was able to get TMDS33 to work with 3.3V 50 Ohm pullup resistors. Any help on this would be greatly appreciated. This is my full constraints file: set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports RESET] #IO_L4N_T0_35 Sch=btn[0] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_p[0]}] #IO_L12P_T1_MRCC_34 Sch=ja_p[3] set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_n[0]}] #IO_L12N_T1_MRCC_34 Sch=ja_n[3] This image shows all that I have in this design. I am trying to use the Vivado block diagram IP designer to instantiate the buffers, and the schematic and device view from implementation shows that the buffer is connected in the design, so I don't think the router/synthesizer is throwing it out. CLKT is using the port interface "xilinxcom:interface:diff_clock_rtl:1.0". Reset is hooked up to button 0 on this board, sys_clock is the 125MHz system clock on H16. The utility buffer IP here is configured to use an OBUFDS. Considering I was able to get TMDS working with the pullup resistors it could be an issue with termination. I've tried it a few different ways without really seeing any output from it as well. here are the two I've tried. My initial goal was to try and serialize parallel data from the PL, output it over LVDS on some wires back into the PL with SERDES primitives and see how fast I could get reliable transmission, but I'm not able to get any LVDS out, so I need to solve that bit first. I do have two of these devices, so it would be fun to transmit from one to the other as well.
  2. Hello eveyone, I am working on TLC5940 to drive LEDs with FPGA cyclone V DE10; Could any one here help me with a VHDL code to activate leds via FPGA? I would be so gratefull. Many thanks in advance
  3. I don't understand why there are, an Arty A7 and Nexys A7 - for FPGA training which is better ? Are both complete, that is is there any additional software costs, or any additional cost(s) to get either one to work ? I need to purchase soon. Thanks Steve
  4. I'm following along with the instruction provided on the GitHub ( to test the functionality of the Zybo board's HDMI ports. I followed the instruction to the T but cannot seem to get a signal to pass through. At first, I connected my cable box to the HDMI Rx and then I switched to my laptop. In both instances, not only did my TV monitor not detect a signal, but the output on the sdk terminal was that the HDMI-in was unplugged (see first attached photo). The HDP / LD9 LED near the HDMI port turns on, telling me it is detecting a signal. Using the Zybo-Z7 reference manual, I deduced that it might be due to an issue with resolution, but if I try to change the resolution, I get 'stuck' in that menu (see second attached photo) and have to restart the processes by clicking run-as -> Launch on Hardware. I also notice the clock frequency is set to 0, but I'm not exactly sure what could be the issue. I have also attached the block design and xdc file as I'm assuming the issue could be there since the pixel clock isn't running. design_1.pdf Zybo-Z7-Master.xdc
  5. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <= 0; sclk <= 0; end else begin count <= count + 1; if(count == 1) begin sclk <= ~sclk; count <= 0; end end end endmodule __ `timescale 1ns / 1ps module spi0( input clock, input reset, input send, output sclk0, output reg cs, output reg ldac, output reg din ); reg[15:0] data [3:0]; reg[15:0] count; reg [1:0] sel; sclk sclk_inst ( .clock(clock), .reset(reset), .sclk(sclk0) ); initial begin data[0] = 16'b0101111000010101; data[1] = 16'b1000011111100001; count = 16'd16; cs = 1; sel = 0; end always @ (negedge sclk0 & send == 1)begin if (send == 1)begin if ( count > 0)begin cs = 0; ldac = 0; end if (count == 0)begin cs = 1; ldac = 1; count = 16'd16; end din = data[sel][count-1]; count = count - 1; end end endmodule __ `timescale 1ns / 1ps module spi0_testbench(); reg clock = 0; reg reset = 0; reg send = 0; reg [50:0]counter = 0; reg [16:0] i; wire sclk0; wire cs; wire ldac; wire din; wire[15:0] count; spi0 UUT(clock, reset, send, sclk0, cs, ldac, din); always @ (*)begin #10 if (i >= 127 & i < 129)begin send = 0; end if (i < 127 | i >= 129) begin send = 1; end if (i < 127)begin end end initial begin for (i = 0; i < 1000; i = i + 1)begin clock = ~clock; counter = counter + 1; #1; end end endmodule Green: SCLK Yellow: DIN Blue: CS Pink: LDAC
  6. I left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. The computer's device manager shows that something is plugged in, but Adept and Vivado are unable to recognize that a device is connected. I was planning to restore the board to it's default setting on Vivado by using a .bin file but received the following error message: "ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Common 17-39] 'open_hw_target' failed due to earlier err." I used a voltmeter to test the voltage across the on/off switch and was getting around 3.3V but now get 0.003V. When I tested the switches that control the on-board LEDS, the also produced around 0.003V. Is there a solution to help me with this as the board is brand new?
  7. Hello, I'm new to this form, looking for some help with the Dual H bridge PMOD DHB1. I connected my power supplier to J4, my motors to J5 and J6. I have a custom IP that uses switches to drive motor speed with most significant bits of a duty cycle for PWM output at 2kz. I also have 2 switches connected to the DIR1 and DIR2 respectively. I also have button 3 connected to a reset condition to initialize code, inputs and outputs. To help debug, I connected the EN1 and EN2 output of the custom IP to the board LEDs to confirm that the signals are working correctly. I also checked the voltage at EN1 and appears to be doing what I expect. However, I do not have any motor actuation. I checked the voltage at the J4 = 8V, but neither J5 or J6 have any voltage differential between M+ and M-. I checked the sleep and fault pins they are both high, which is normal behavior as they are pulled low when in sleep or faulted state. Any advice on what I can do to find an issue would be appreciated. Thanks, Dave HBridgeTOP Hbridgecode (1)
  8. Hello! I am working on implementing the IBERT IP core on the Genesys2 dev board. I have purchased this daughter board to connect to the FMC, but I am unsure of how the pins relate to the SMA connectors. Has anyone used this daughter board before? I have emailed Hitech Global for documentation, but I have not received a response as of yet. Also, does anyone know if a guide such as this one exists for the Genesys2 board? I assume that the steps would be very similar since they both use the Kintex-7 FPGA. Thanks
  9. Hi, I am trying to generate a pulse wave instead of a continuous wave which is the default of Waveform Live. Is there a way to do this? I am also having a problem using the math function which is located in the bottom right of the browser, It freezes the site when it is selected.