Tri-Mode Ethernet MAC LogiCORE IP? Ethernet without the PS?

[davwamai]

I've been looking around for ways to transfer ZMOD ADC samples through ethernet (or literally any other way other than UART/SD because it is very slow for my particular application) on the Eclypse Z7 board. It seems like the only option is to use an altered version of the several lwIP examples provided in SDK/Vitis. For someone with limited experience in networking, like myself, this seems like a path of great resistance. Upon trying the demo, I quickly ran into issues such as the connection routine failing to perform a successful handshake with the board. Part of me realizes that it's time to be a big boy and learn the nuances of TCP/UDP, but I'd like to evaluate any and all possible options before I get around to it. 

Google presented to me what looked like my saving grace, the Tri-Mode Ethernet MAC LogiCORE IP in the form of a super neat example project done by fpgadeveloper. He was able to get the IP to do some cool tricks, like interfacing with a separate breakout board to provide the user with four different ethernet ports. 

The coolest part, though, was the fact that an ethernet connection (from what I can understand) is possible without the use of the PS. I got really excited at this news, as I am trying to develop a real-time analog signal acquisition and processing system, and this IP block advertising an Ethernet connection using programmable logic alone seems to be as 'real-time' as it gets. Keep in mind that I've been doing FPGA development as an undergrad student for maybe half a year, so it is more than possible that I completely misunderstood the intended applications of the IP and how it can benefit my own application. 

FPGAdeveloper's IP bring-up process was an Inception style example within an example, assembled for the KC705 and AC701 to interface with their on-board general purpose switches and push buttons. His walkthrough got the IP up and running (on a board I do not own), but I was still unsure as to how the thing worked. This lead me to the Product Guide, where I quickly realized I was way in over my head when I began to read the hieroglyphics that is probably incredibly useful to someone who knows what their doing. 

I looked around for other implementations involving similar hardware and purposes to no avail, so I decided to get my hands dirty and opened up the IP in Vivado to see if I could get an idea of how it worked. In short, I still don't get it (shocker). I started with going pin-by-pin and Googling their possible usages. It seems like the left side of the IP interfaces with an AXI EthernetLite block for data transmission, but that's really all was able to deduce. Maybe some pins should be externalized to allow DDR interfacing through EMIO, but which ones exactly are a mystery to me. 

I will continue to brute force an understanding of the IP by staring at the product guide until I get it. Until then, I was wondering if anyone could provide any insight on how one would use this IP to send ZMOD ADC data through ethernet to a host PC, or crush my dreams and explain to me why it's not possible. Surely it's too good to be true, but this last glimmer of hope, I feel, is still worth looking into before I resort to lwIP. 

Edited June 16, 2023 by davwamai
added tags

[zygot]

2 hours ago, davwamai said:

The coolest part, though, was the fact that an Ethernet connection (from what I can understand) is possible without the use of the PS.

Of course you can use an Ethernet PHY to connect things without a processor.  The PHY is essentially a standalone cable modem with an interface that can be as simple as a DDR interface or complicated as a transceiver interface. You don't need a MAC either, regardless of what the FPGA vendors want you to believe. For 1 GbE or greater data rates it sure is easier to have a PHY that's accessible by logic. In the case of the Eclypse-Z7 there's no Ethernet PHY on the board that the PL has access to. There is another option, if you can make do with using just one of the SYZYGY ports for ADC or DAC functionality; Opal Kelly sells a 1 GbE Ethernet PHY pod with a SYZYGY interface. This means that you can acquire ADC samples and transfer them off of the board without the PS even being aware of any of it. Essentially, you are turning the Z7020 into an A75 device. I've used this pod and can say that it works. The problem is that all of the FPGA vendors really, really don't want you to use an Ethernet PHY functionality without a processor so they make such hardware as hard to use as possible.

An alternate way to transfer data between your Eclypse-Z7 and a PC would be to use the very odd PMOD design. It is possible to connect a FT4232H module to 2 PMODs and have 4 12 Mbaud UART channels connecting your 2 ADC or DAC devices to a PC directly. No this isn't close to the 120+ MiB/s of a 1 GbE Ethernet PHY, but it's a possibility and one that might be easier to implement. 3-5 MiB/s is better than 0 MiB/s.

The ZYNQ GEM is difficult to work with, especially if you aren't running a version of Linux on your PS cores. Doing it in hardware is less convoluted, but requires a fair bit of knowledge about Ethernet packet structures and a solid digital design capability. The nice thing about doing it in hardware is that you can control all of your source code and not rely on any vendor IP.

As to how the Opsero Ethernet cards are going to help you with you Eclypse-Z7 I'm baffled as, except for the Opa Kelly SYZYGY Ethernet pod, there's no way to connect to such a board. I've used one of Opsero's FMC Ethernet boards, and it's a well designed and supported product though I don't use any of their demo projects for reason that are beyond the scope of this post.

My advice is to take the time to learn about Ethernet layers. For simple point to point communication, you only need a couple of packet types to connect with a PC. It did take me about 1 year to learn enough to be productive. Most people are smarter than I am.

For the HDL implementation of Ethernet I'd suggest using a platform more suitable.. just about any FPGA board with a 1 GbE Ethernet PHY should do. You might want to start with a soft-processor implementation and then start working on a second project that doesn't include either a processor or MAC.

Edited June 16, 2023 by zygot