Custom PCB with Spartan7 and DDR2 ...

[moreasm]

Hi, I'm new to the forum.

I'm making a new PCB using a Spartan7 and a DDR2 "MT47H64M16NF-25E". It's the first time I've made a PCB with DDR2, so I took the "Nexys A7" board as a reference schematics.

Unfortunately no gerbers or PCB view are available, so I searched for all possible documentation on the internet to draw the DDR2 interface.

I have grouped the signals as reported by different guides:

# Clock
CLK_P/CLK_N

# Address and Control
ADDRESS[0:12]
BA[0:2]
CAS
RAS
WE

# Data Low
DATA[0:7]
LDM
LDQS_P/LDQS_N

# Data High
DATA[8:15]
UDM
UDQS_P/UDQS_N

# Others
CS
CKE
ODT

The same guides recommend making the tracks with an impedance of 50 Ohm (+/- 10%) for the single-ended tracks and 100 Ohm (+/- 10%) for the differential tracks.

The lengths of the tracks must all be the same, using "Switchback pattern" to achieve the same length.

It is recommended to lengthen the differential clock by 25 mils.

Some guides recommend the "VTT" termination of the "Controls", but I'm not sure when this should be done. The "Nexys A7" board does not have the "VTT" termination and the frequency of 650 MHz can be reached.

When should the "VTT" termination be used ?

Do you have any additional guidance/advice for me ?

Thanks very much.

moreasm

[asmi]

7 hours ago, moreasm said:

Thanks very much for your reply. Your project was already on my dashboard, it's the only one that allowed me to physically see the PCB of a DDR2 and look for some confirmation. Unfortunately the Kicad is not ideal for certain types of realizations (measurement of lengths, tuning of tracks, etc.) however it clarified several aspects for me.

There is a trick to it which I actually used to tune trace length - if you select the trace in KiCAD, it will show you the current length of a trace in the status bar.

 

As for length tuning rules, I thought they are pretty clearly outlined in the MIG user guide. Here are the gist of them:

1. All traces are subdivided into length matching groups, and they only need to be matched inside the group, not neccessarily with other groups. Address and control signals (Axx and BAx lines, RAS/CAS/WE/CKE/ODT and CK/CK#) form a single group, and each byte lane (8 data lines, DQS/DQS# and DM) form a separate byte group.

2. Within each byte group traces need to be matched to 20 ps (so ±10 ps from reference length)

3. Address/control group need to be matched to 50 ps (±25 ps)

4. Address/control group need to be at least as long as the longest byte group.

5. Each differential pair (CK/CK#, DQSx/DQSx#) need to be matched to about 5 ps

6. Do your best to route each group the same way - using the same layers, same amount of vias, etc. If it's not possible, remember that a) signals on outer layers travel faster than on internal layers, and b) if vias are not used uniformly in a group then they add additional delays. This is why abovementioned rules are set in units of time as opposed to units of length. Most modern commercial eCAD tools can work with time units for matching as well as length units, so I highly recommend setting up rules in terms of time.

7. To help with routing, you can swap around pins for bit signals within each byte group, and address/control signals (again within the group). You can also swap around entire byte lane groups between each other (for example connect byte lane 0 of FPGA to DDR's byte lane 1 and vice versa). You can NOT swap lines from different groups, and you also can NOT swap positive and negative lines of differential pairs.

8. I used 50 Ohm impedance for single-ended signals and 100 Ohm differential impedance for differential pairs. MIG user guide specifies 50/100 Ohm for DDR2/DDR3 interfaces up to 533 Mhz, and 40/80 for higher frequencies.

 

Now, specifically for Spartan-7 and DDR2 the interface speed is going to be rather slow (depending on package and speed grade, it will be 333 or 400 MHz), so a lot of these rules can be somewhat relaxed. For example, in my project's PCB layout I forgot to take via Z-length into account during length matching, and the interface still works just fine. But the higher the frequency (this mostly applies to DDR3 which can go as fast as 933 MHz per JEDEC), the more strict those rules become, which is why I strive to obey them to the best of my abilities. Now, again in that project the goal was to make the project as affordable to build as possible, which is why I went for 4 layer PCB, but generally I highly recommend going for at least 6 layers, but preferably 8 because you can take full advantage of plane capacitance and route your high-speed traces on internal layers so improving EMI/EMC.

Finally, before you get on with layout at all, create a test design in Vivado to make sure the pinout you've chosen will actually work, and update the DDRx pinout to the one you actually have after all pin swapping once your complete layout to confirm the same. You can also use that design later to perform initial hardware checkout once you have the assembled board.

Good luck and let me know if your have any further questions.

Edited December 8, 2022 by asmi

[JColvin]

Hi @moreasm,

Unfortunately, Digilent does not provide the gerbers for our boards and is not (or at least I am not) able to offer any direct help for designing your own setup outside of directing you to the existing Xilinx documentation which I imagine you have already seen. Hopefully you will be able to get some insight from other Forum users.

Thanks,
JColvin

[moreasm]

Hi,

In fact, I was waiting for an answer from some more expert users on the matter.

I wait patiently.

Thank you very much.

moreasm

[asmi]

You can take a look at my project with Spartan-7 and DDR2 for details here: https://www.eevblog.com/forum/fpga/custom-spartan-7-board-for-beginners/ It's made in KiCAD and it's an open hardware, so you are free to mess with it however you want.

Now, onto your questions:

1. For a single module all connections are point-to-point and so you can get away without termination for address/control signals. You will still need a 100 Ohm differential termination resistor for the differential clock. So you can use internal VTT in MIG settings as well, which will save you some pins, which is valuable.

2. Nexus A7 can not possibly reach 650 MHz because Artix-7 can only drive DDR2 up to 400 MHz.

3. You can find answers for a lot of your questions in the Xilinx MIG user guide UG586. Specifically chapter 1, section Design Guidelines -> DDR2 SDRAM

Good luck with your design!

[moreasm]

Hi asmi,

Thanks very much for your reply. Your project was already on my dashboard, it's the only one that allowed me to physically see the PCB of a DDR2 and look for some confirmation. Unfortunately the Kicad is not ideal for certain types of realizations (measurement of lengths, tuning of tracks, etc.) however it clarified several aspects for me.

On 12/6/2022 at 11:00 PM, asmi said:

1. For a single module all connections are point-to-point and so you can get away without termination for address/control signals. You will still need a 100 Ohm differential termination resistor for the differential clock. So you can use internal VTT in MIG settings as well, which will save you some pins, which is valuable.

I was what I wanted to hear, I had many doubts about it, now I'm calmer.

On 12/6/2022 at 11:00 PM, asmi said:

2. Nexus A7 can not possibly reach 650 MHz because Artix-7 can only drive DDR2 up to 400 MHz.

Sorry I got confused between 650Mbps and 650MHz. As you can clearly read here:

https://digilent.com/reference/programmable-logic/nexys-a7/reference-manual#ddr2

The clock used is 1/3.077 ps = 325 MHz equivalent to 650 Mbps.

On 12/6/2022 at 11:00 PM, asmi said:

3. You can find answers for a lot of your questions in the Xilinx MIG user guide UG586. Specifically chapter 1, section Design Guidelines -> DDR2 SDRAM

Of course I read this too, I also read WP484. Thank you.

What I ask you, however, is if you followed any precise pattern during the routing, any particular technique and how you considered and adjusted the length of the tracks of the various groups. How did you calculate the impedances of the tracks ? What impedances did you choose and use ? What other considerations did you make ?

Did you use a table like this or something similar:

Thanks so much for your advice.

moreasm

DDR Layout Guide - (cinese).pdf ISSI DDR2 SDRAM Design Considerations Guide.pdf TN-46-14 Hardware Tips for Point-to-Point System Design.pdf

[moreasm]

Hi asmi,

On 12/8/2022 at 6:18 PM, asmi said:

There is a trick to it which I actually used to tune trace length - if you select the trace in KiCAD, it will show you the current length of a trace in the status bar.

Perfect, it's a great find.

The eight points you listed are roughly the ones I was just drafting, gathering information around. Point number "8" is clear enough, I wonder which tool you used to calculate the Microstrip and Stripline impedances. I searched the internet for tools but each returns a different value.

On 12/8/2022 at 6:18 PM, asmi said:

Finally, before you get on with layout at all, create a test design in Vivado to make sure the pinout you've chosen will actually work, and update the DDRx pinout to the one you actually have after all pin swapping once your complete layout to confirm the same. You can also use that design later to perform initial hardware checkout once you have the assembled board.

This is something I did several times to verify that everything could actually work. I finished the initial routing for all the signals, I just needed confirmations from those who had already done something similar to proceed with the tuning correctly.

Your advice has been really very useful and I imagine that at this point, given the detailed post, it will also be useful for someone else who wants to try their hand at the same enterprise.

I thank you infinitely.

moreasm

[asmi]

2 hours ago, moreasm said:

Point number "8" is clear enough, I wonder which tool you used to calculate the Microstrip and Stripline impedances. I searched the internet for tools but each returns a different value.

Since that PCB was designed around JLCPCB's process, I just took values from their impedance calculator (at the time). Nowadays most commercial tools have built-in field solvers to do these calculations for you, at least the two commercial tools I used - Altium Designer and Orcad PCB Editor Professional - have them, so that's what I use. In general it's best to ask your fabricator if you are unsure as they are the one who will ultimately be making these boards so they know the best what trace parameters should be. Small bit of advice here - when rounding your calculated parameters, always round UP as opposed to round-to-nearest, because manufacturers can adjust trace width by themselves during pre-production to achieve requested impedance, and it's much easier to make traces narrower than they are, then the opposite - as the latter is not always possible due to possible violations of trace-to-trace spacing, not to mention potential crosstalk problems.

  

2 hours ago, moreasm said:

I thank you infinitely.

moreasm

You are most welcome! Good luck!

Edited December 9, 2022 by asmi