moreasm

Hi asmi, Perfect, it's a great find. The eight points you listed are roughly the ones I was just drafting, gathering information around. Point number "8" is clear enough, I wonder which tool you used to calculate the Microstrip and Stripline impedances. I searched the internet for tools but each returns a different value. This is something I did several times to verify that everything could actually work. I finished the initial routing for all the signals, I just needed confirmations from those who had already done something similar to proceed with the tuning correctly. Your advice has been really very useful and I imagine that at this point, given the detailed post, it will also be useful for someone else who wants to try their hand at the same enterprise. I thank you infinitely. moreasm

Hi asmi, Thanks very much for your reply. Your project was already on my dashboard, it's the only one that allowed me to physically see the PCB of a DDR2 and look for some confirmation. Unfortunately the Kicad is not ideal for certain types of realizations (measurement of lengths, tuning of tracks, etc.) however it clarified several aspects for me. I was what I wanted to hear, I had many doubts about it, now I'm calmer. Sorry I got confused between 650Mbps and 650MHz. As you can clearly read here: https://digilent.com/reference/programmable-logic/nexys-a7/reference-manual#ddr2 The clock used is 1/3.077 ps = 325 MHz equivalent to 650 Mbps. Of course I read this too, I also read WP484. Thank you. What I ask you, however, is if you followed any precise pattern during the routing, any particular technique and how you considered and adjusted the length of the tracks of the various groups. How did you calculate the impedances of the tracks ? What impedances did you choose and use ? What other considerations did you make ? Did you use a table like this or something similar: Thanks so much for your advice. moreasm DDR Layout Guide - (cinese).pdf ISSI DDR2 SDRAM Design Considerations Guide.pdf TN-46-14 Hardware Tips for Point-to-Point System Design.pdf

Hi, In fact, I was waiting for an answer from some more expert users on the matter. I wait patiently. Thank you very much. moreasm

Hi, I'm new to the forum. I'm making a new PCB using a Spartan7 and a DDR2 "MT47H64M16NF-25E". It's the first time I've made a PCB with DDR2, so I took the "Nexys A7" board as a reference schematics. Unfortunately no gerbers or PCB view are available, so I searched for all possible documentation on the internet to draw the DDR2 interface. I have grouped the signals as reported by different guides: # Clock CLK_P/CLK_N # Address and Control ADDRESS[0:12] BA[0:2] CAS RAS WE # Data Low DATA[0:7] LDM LDQS_P/LDQS_N # Data High DATA[8:15] UDM UDQS_P/UDQS_N # Others CS CKE ODT The same guides recommend making the tracks with an impedance of 50 Ohm (+/- 10%) for the single-ended tracks and 100 Ohm (+/- 10%) for the differential tracks. The lengths of the tracks must all be the same, using "Switchback pattern" to achieve the same length. It is recommended to lengthen the differential clock by 25 mils. Some guides recommend the "VTT" termination of the "Controls", but I'm not sure when this should be done. The "Nexys A7" board does not have the "VTT" termination and the frequency of 650 MHz can be reached. When should the "VTT" termination be used ? Do you have any additional guidance/advice for me ? Thanks very much. moreasm