PMOD DA4 interface with Atlys (spartan 6 ) FPGA

[Gopal Krishna]

I am trying to interface PMOD DA4 with atlys FPGA but nothing is coming at output. help me to rectify what wrong with code. 

 

module spi_master_v1(
    input sys_clk,
    input rst,
    output reg cs,
    output reg MOSI,
    output reg sclk,
//    input [31:0] in_data,
    output reg done
    );
    
    // Internal registers
    reg [10:0] count;
    reg [31:0] temp_data;
    reg [5:0] bit_count;
    reg [11:0] count2;
    

    
    // state declearation
    reg [1:0] state;
    parameter idle = 2'b00;
    parameter data_tx = 2'b01;
    parameter finish = 2'b10;
    
        //initialize all register
    
    initial begin
        cs = 1;
        MOSI = 0;
        sclk = 0;
        done = 0;
        count = 0;
        temp_data =32'b00000000000000000000000000000000;
        bit_count = 0;
        state = 0;
        count2 = 0;
    end
    
    // clock dividwer
    always @(posedge sys_clk)
        begin
            if (count == 4)
                begin
                    sclk <= ~sclk;
                    count <= 11'b00000000000;
                end
            else
                begin
                    count = count +1;
                end
        end
    
    // functional design
    
    always @(posedge sclk)
        begin
            case (state)
                idle :
                    begin
                        done = 1'b0;
                        cs = 1'b1;
                        state = data_tx;
                        temp_data[7:0] = 8'b00000000;
                        temp_data[19:8] = count2;
                        temp_data[31:20] = 12'b100000001111;
                        MOSI = 0;
                        count2 = count2 + 1;
                        
                    end
                    
                    
                data_tx:
                    begin
                        
                        cs = 1'b0;
                        MOSI = temp_data[31-bit_count];
                        
                        if (bit_count == 32)
                            begin
                                state = finish;
                                bit_count = 0;
                                done = 1'b1;
                                MOSI = 0;
                            end
                        else 
                            begin
                                bit_count = bit_count + 1;
                            end
                        
                    end
                    
                    
                finish:
                    begin
                        cs = 1'b1;
                        state = idle;
                        MOSI = 0;
                    end
               
            endcase
        end
    
endmodule
 

[JColvin]

Hi @Gopal Krishna,

Did you configure the chip in the Pmod DA4 to use it's internal reference voltage rather than it's (non-existent) external reference voltage? The 32 bits of data that would need to be initially sent in order to have the Pmod use it's 1.25V reference voltage is 0x8001 (32'b00001000000000000000000000000001). You'll also need to make sure that you both update the input registers and update the DAC registers, or do both simultaneously by using one of the commands listed in Table 9 of the AD5628 datasheet.

I'm not sure what your sys_clk is running at, but as long as the serial clock of the Pmod is less than 50 MHz (the maximum listed on the AD5628 datasheet), you should be okay.

There is also a similar forum thread that worked with the Pmod DA4 that may be of interest to you here.

Thanks,
JColvin

[Gopal Krishna]

On 3/3/2021 at 7:11 AM, JColvin said:

Hi @Gopal Krishna,

Did you configure the chip in the Pmod DA4 to use it's internal reference voltage rather than it's (non-existent) external reference voltage? The 32 bits of data that would need to be initially sent in order to have the Pmod use it's 1.25V reference voltage is 0x8001 (32'b00001000000000000000000000000001). You'll also need to make sure that you both update the input registers and update the DAC registers, or do both simultaneously by using one of the commands listed in Table 9 of the AD5628 datasheet.

I'm not sure what your sys_clk is running at, but as long as the serial clock of the Pmod is less than 50 MHz (the maximum listed on the AD5628 datasheet), you should be okay.

There is also a similar forum thread that worked with the Pmod DA4 that may be of interest to you here.

Thanks,
JColvin

Thank you @JColvin

 

Thank you very much for your reply, your earlier post regrading PMOD DA4 was really very helpful. NOW my DA4 is working fine with Atlys FPGA.

  Do you have any idea about how to configure atlys FPGA ethernet port to transmit and receive data from computer??

 

--

Thanks 

Gopal